User guide

RLDRAM II
RLDRAM II is the second generation of
RLDRAM. It is a development of DDR SDRAM,
designed to address the low latency
requirements of certain applications, such as
packet buffers in high-performance line cards.
RLDRAM II has a high-performance DDR data
bus and offers a non-multiplexed address bus,
reducing the number of clock cycles to initiate
read or write applications. A banked
architecture also reduces access time. In some
systems, RLDRAM II eliminates the need for
specialized content-addressable memory (CAM)
or SRAM.
RLDRAM III
RLDRAM III is the third generation of
RLDRAM. It is a development of DDR SDRAM,
designed to address the low latency
requirements of certain applications, such as
packet buffers in high-performance line cards.
RLDRAM III has a high-performance DDR data
bus and offers a non-multiplexed address bus,
reducing the number of clock cycles to initiate
read or write applications. A banked
architecture also reduces access time. In some
systems, RLDRAM III eliminates the need for
specialized content-addressable memory (CAM)
or SRAM.
SDR DRAM
SDR SDRAM is the first generation of
synchronous DRAM. It improves memory
bandwidth over extended data out (EDO) DRAM
by offering data transfer up to once-per-clock
cycle.
SRAM Device Overview
Altera provides a complete system solution to help you successfully interface Altera® FPGAs and
HardCopy® ASICs to a variety of SRAM devices. SRAM devices offer extremely fast access times —
approximately four times faster than DRAM — but are much more expensive to produce. Unlike DRAM,
SRAM does not need to be refreshed periodically to prevent data loss through leakage. SRAM devices are
capable of storing data as long as the device is supplied with power. If the power is turned off, the contents
are lost. Typical systems require both SRAM (for performance-critical applications) and DRAM memory (for
all other applications).
QDR and QDR II SRAM Devices
QDR memory devices allow two ports to run
independently at DDR, which results in four
data items per clock cycle. QDR SRAMs enable
you to maximize bandwidth by allowing
operation at data rates above 200MHz. The QDR
architecture allows you to reach these speeds
without the possibility of bus contention.
The QDR consortium, which consists of Cypress
Semiconductor, Integrated Device Technology
(IDT), Micron Technology, and NEC Corporation,