Specifications

CY14C101PA
CY14B101PA
CY14E101PA
Document Number: 001-54392 Rev. *N Page 38 of 44
Switching Waveforms
Figure 42. Hardware STORE Cycle
[28]
Hardware STORE Cycle
Over the Operating Range
Parameter Description
CY14X101PA
Unit
Min Max
t
PHSB
Hardware STORE pulse width 15 – ns
~
~
HSB (IN)
HSB (OUT)
RWI
HSB (IN)
HSB (OUT)
RWI
t
HHHD
t
STORE
t
PHSB
t
DELAY
t
LZHSB
t
DELAY
t
PHSB
HSB pin is driven HIGH to V
CC
only by Internal
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
Write Latch not set
Write Latch set
~
~
~
~
~
~
Note
28. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.