Specifications

CY14C101PA
CY14B101PA
CY14E101PA
Document Number: 001-54392 Rev. *N Page 36 of 44
AutoStore or Power-Up RECALL
Over the Operating Range
Parameter Description
CY14X101PA
Unit
Min Max
t
FA
[20]
Power-up RECALL duration CY14C101PA – 40 ms
CY14B101PA – 20 ms
CY14E101PA – 20 ms
t
STORE
[21]
STORE cycle duration – 8 ms
t
DELAY
[22]
Time allowed to complete SRAM write cycle – 25 ns
V
SWITCH
Low voltage trigger level CY14C101PA – 2.35 V
CY14B101PA – 2.65 V
CY14E101PA – 4.40 V
t
VCCRISE
[23]
V
CC
rise time 150 – µs
V
HDIS
[23]
HSB output disable voltage – 1.9 V
t
LZHSB
[23]
HSB high to nvSRAM active time – 5 µs
t
HHHD
[23]
HSB HIGH active time – 500 ns
t
WAKE
Time for nvSRAM to wake up from SLEEP mode CY14C101PA – 40 ms
CY14B101PA – 20 ms
CY14E101PA – 20 ms
t
SLEEP
Time to enter into SLEEP mode after Issuing SLEEP instruction – 8 ms
t
SB
[23]
Time to enter into standby mode after CS going HIGH – 100 µs
Switching Waveforms
Figure 37. AutoStore or Power Up RECALL
[24]
V
SWITCH
V
HDIS
t
VCCRISE
t
STORE
t
STORE
t
HHHD
t
HHHD
t
DELAY
t
DELAY
t
LZHSB
t
LZHSB
t
FA
t
FA
HSB OUT
AutoStore
POWER-
UP
RECALL
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write
BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write
POWER
DOWN
AutoStore
Note
Note
Note
Note
V
CC
21
21
25
25
Notes
20. t
FA
starts from the time V
CC
rises above V
SWITCH
.
21. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
22. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time t
DELAY
.
23. These parameters are guaranteed by design and are not tested.
24. Read and Write cycles are ignored during STORE, RECALL, and while V
CC
is below V
SWITCH
.
25. During power-up and power-down, HSB
glitches when HSB pin is pulled up through an external resistor.