Specifications

CY14C101PA
CY14B101PA
CY14E101PA
Document Number: 001-54392 Rev. *N Page 26 of 44
PCB Design Considerations for RTC
RTC crystal oscillator is a low current circuit with high impedance
nodes on their crystal pins. Due to lower timekeeping current of
RTC, the crystal connections are very sensitive to noise on the
board. Hence it is necessary to isolate the RTC circuit from other
signals on the board.
It is also critical to minimize the stray capacitance on the PCB.
Stray capacitances add to the overall crystal load capacitance
and therefore cause oscillation frequency errors. Proper
bypassing and careful layout are required to achieve the
optimum RTC performance.
Layout requirements
The board layout must adhere to (but not limited to) the following
guidelines during routing RTC circuitry. Following these guide-
lines help you achieve optimum performance from the RTC
design.
■ It is important to place the crystal as close as possible to the
X
in
and X
out
pins. Keep the trace lengths between the crystal
and RTC equal in length and as short as possible to reduce the
probability of noise coupling by reducing the length of the
antenna.
■ Keep X
in
and X
out
trace width lesser than 8 mils. Wider trace
width leads to larger trace capacitance. The larger these bond
pads and traces are, the more likely it is that noise can couple
from adjacent signals.
■ Shield the X
in
and X
out
signals by providing a guard ring around
the crystal circuitry. This guard ring prevents noise coupling
from neighboring signals.
■ Take care while routing any other high speed signal in the
vicinity of RTC traces. The more the crystal is isolated from
other signals on the board, the less likely it is that noise is
coupled into the crystal. Maintain a minimum of 200 mil
separation between the X
in
, X
out
traces and any other high
speed signal on the board.
■ No signals should run underneath crystal components on the
same PCB layer.
■ Create an isolated solid copper plane on adjacent PCB layer
and underneath the crystal circuitry to prevent unwanted noise
coupled from traces routed on the other signal layers of the
PCB. The local plane should be separated by at least 40 mils
from the neighboring plane on the same PCB layer. The solid
plane should be in the vicinity of RTC components only and its
perimeter should be kept equal to the guard ring perimeter.
Figure 33
shows the recommended layout for RTC circuit.
Figure 33. Recommended Layout for RTC
Isolated ground plane on
Guard ring - Top (Component)
Via: Via connects to isolated
ground plane on L2
Via: Via connects to system ground
plane on L2
layer 2 : L2
layer: L1
System ground
Top component layer: L1
Ground plane layer: L2
C1
Y1
C2