Specifications

CY14C101PA
CY14B101PA
CY14E101PA
Document Number: 001-54392 Rev. *N Page 24 of 44
High/Low (H/L): When set to a ‘1’, the INT pin is active HIGH
and the driver mode is push pull. The INT pin drives HIGH only
when V
CC
is greater than V
SWITCH
. When set to a ‘0’, the INT pin
is active LOW and the drive mode is open drain. The INT pin
must be pulled up to Vcc by a 10 k resistor while using the
interrupt in active LOW mode.
Pulse/Level (P/L): When set to a ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to a
‘0’, the INT pin is driven HIGH or LOW (determined by H/L) until
the flags register is read.
SQ1 and SQ0. These bits are used together to fix the frequency
of square wave on INT pin output when SQWE bit is set to ‘1’.
These bits are nonvolatile and survive power cycle. The output
frequency is decided as per the following table.
When an enabled interrupt source activates the INT pin, an
external host reads the flag registers to determine the cause.
Remember that all flag are cleared when the register is read. If
the INT pin is programmed for Level mode, then the condition
clears and the INT pin returns to its inactive state. If the pin is
programmed for pulse mode, then reading the flag also clears
the flag and the pin. The pulse does not complete its specified
duration if the flags register is read. If the INT pin is used as a
host reset, the flags register is not read during a reset.
This summary table shows the state of the INT pin.
Flags Register
The flags register has three flag bits: WDF, AF, and PF, which
can be used to generate an interrupt. These flag are set by the
watchdog timeout, alarm match, or power fail monitor
respectively. The processor can either poll this register or enable
interrupts to be informed when a flag is set. These flags are
automatically reset after the register is read. The flags register is
automatically loaded with the value 0x00 on power-up (except
for the OSCF bit. See Stopping and Starting the Oscillator on
page 21).
Table 9. SQW Output Selection
SQ1 SQ0 Frequency Comment
0 0 1 Hz 1 Hz signal
0 1 512 Hz Useful for calibration
1 0 4096 Hz 4 kHz clock output
1 1 32768 Hz Oscillator output
frequency
Table 10. State of the INT pin
CAL SQWE
WIE/AIE/
PFE
INT Pin Output
1 X X 512 Hz
0 1 X Square Wave
Output
00 1 Alarm
00 0 HI-Z
Figure 31. Interrupt Block Diagram
WDF - Watchdog Timer Flag
WIE - Watchdog Interrupt
PF - Power Fail Flag
PFE - Power Fail Enable
AF - Alarm Flag
AIE - Alarm Interrupt Enable
P/L - Pulse Level
H/L - High/Low
Enable
Pin
Driver
WIE
WDF
Watchdog
Timer
PFE
PF
AIE
AF
Clock
Alarm
P/L
H/L
V
CC
V
SS
INT
SQWE
CAL
Mux
512 Hz
Clock
Square
Wave
Priority
Encoder
WIE/PIE/
AIE
HI-Z
Control
SEL Line
Power
Monitor
SQWE - Square wave enable