Specifications

ManualsBrandsCypress Semiconductor ManualsComputer equipmentCY7C1356CV25

CY14C101PA

CY14B101PA

CY14E101PA

Document Number: 001-54392 Rev. *N Page 15 of 44

RTC Access

CY14X101PA uses 16 registers for RTC. These registers can be

read out or written to by accessing all 16 registers in burst mode

or accessing each register, one at a time. The RDRTC,

FAST_RDRTC, and WRTC instructions are used to access the

RTC.

All the RTC registers can be read in burst mode by issuing the

RDRTC and FAST_RDRTC instruction and reading all 16 bytes

without bringing the CS

pin HIGH. The ‘R’ bit must be set while

reading the RTC timekeeping registers to ensure that transitional

values of time are not read.

Writes to the RTC register are performed using the WRTC

instruction. Writing RTC timekeeping registers and control

registers, except for the flags register needs the ‘W’ bit of the

flags register to be set to ‘1’. The internal counters are updated

with the new date and time setting when the ‘W’ bit is cleared to

‘0’. All the RTC registers can also be written in burst mode using

the WRTC instruction.

READ RTC (RDRTC) Instruction

Read RTC (RDRTC) instruction allows you to read the contents

of RTC registers at SPI frequency upto 25 MHz. Reading the

RTC registers through the SO pin requires the following

sequence: After the CS

line is pulled LOW to select a device, the

RDRTC opcode is transmitted through the SI line followed by

eight address bits for selecting the register. Any data on the SI

line after the address bits is ignored. The data (D7–D0) at the

specified address is then shifted out onto the SO line. RDRTC

also allows burst mode read operation. When reading multiple

bytes from RTC registers, the address rolls over to 0x00 after the

last RTC register address (0x0F) is reached.

The ‘R’ bit in RTC flags register must be set to ‘1’ before reading

RTC time keeping registers to avoid reading transitional data.

Modifying the RTC flag registers requires a Write RTC cycle. The

R bit must be cleared to '0' after completion of the read operation.

The easiest way to read RTC registers is to perform RDRTC in

burst mode. The read may start from the first RTC register (0x00)

and the CS

must be held LOW to allow the data from all 16 RTC

registers to be transmitted through the SO pin.

Note RDRTC instruction operates at a maximum clock

frequency of 25 MHz. The opcode cycles, address cycles and

data out cycles need to run at 25 MHz for the instruction to work

properly.

Fast Read Sequence (FAST_RDRTC) Instruction

The FAST_RDRTC instruction allows you to read memory at a

SPI frequency above 25 MHz and up to 104 MHz (Max). The host

system must first select the device by driving CS

LOW, the

FAST_READ instruction is then written to SI, followed by 8 bit

address and a dummy byte.

From the subsequent falling edge of the SCK, the data of the

specific address is shifted out serially on the SO line starting with

MSB. The first byte specified can be at any location. The device

automatically increments to the next higher address after each

byte of data is output. The entire memory array can therefore be

read with a single FAST_RDRTC instruction. When the highest

address (0x0F) in the memory array is reached, the address

counter rolls over to start address 0x00 and thus allowing the

read sequence to continue indefinitely. The FAST_RDRTC

instruction is terminated by driving CS

HIGH at any time during

data output.

Note FAST_READ instruction operates up to Max of 104 MHz

SPI frequency.

Figure 16. Read RTC (RDRTC) Instruction Timing

Figure 17. Fast RTC Read (FAST_RDRTC) Instruction Timing

SCK

012345 67

45 67012345 67

MSB LSB

Data

Op-Code

000 1

001

0000

A1A2

MSB

LSB

D2D3

HI-Z

SCK

012345 67

4 5 6 7 8 9 10 11 12 13 14 15