Specifications

CY14C101PA
CY14B101PA
CY14E101PA
Document Number: 001-54392 Rev. *N Page 13 of 44
From the subsequent falling edge of the SCK, the data of the
specific address is shifted out serially on the SO line starting with
MSB. The first byte specified can be at any location. The device
automatically increments to the next higher address after each
byte of data is output. The entire memory array can therefore be
read with a single FAST_READ instruction. When the highest
address in the memory array is reached, address counter rolls
over to start address 0x00000 and thus allowing the read
sequence to continue indefinitely. The FAST_READ instruction
is terminated by driving CS
HIGH at any time during data output.
Note FAST_READ instruction operates up to maximum of
104 MHz SPI frequency.
Write Sequence (WRITE) Instruction
The write operations on CY14X101PA are performed through the
SI pin. To perform a write operation, if the device is write
disabled, then the device must first be write enabled through the
WREN instruction. When the writes are enabled (WEN = ‘1’),
WRITE instruction is issued after the falling edge of CS
. A
WRITE instruction constitutes transmitting the WRITE opcode
on SI line followed by 3-bytes of address and the data (D7–D0)
which is to be written. The most significant address byte contains
A16 in bit 0 with other bits being don’t cares. Address bits A15 to
A0 are sent in the following two address bytes.
CY14X101PA allows writes to be performed in bursts through
SPI which can be used to write consecutive addresses without
issuing a new WRITE instruction. If only one byte is to be written,
the CS
line must be driven HIGH after the D0 (LSB of data) is
transmitted. However, if more bytes are to be written, CS
line
must be held LOW and address incremented automatically. The
following bytes on the SI line are treated as data bytes and
written in the successive addresses. When the last data memory
address (0x1FFFF) is reached, the address rolls over to 0x00000
and the device continues to write.
The WEN bit is reset to ‘0’ on completion of a WRITE sequence.
Note When a burst write reaches a protected block address, it
continues the address increment into the protected space but
does not write any data to the protected memory. If the address
roll over takes the burst write to unprotected space, it resumes
writes. The same operation is true if a burst write is initiated
within a write protected block.
Figure 11. Read Instruction Timing
~
~
CS
SCK
SO
012345 67
0
765432
1
20212223012345 67
MSB LSB
Data
SI
~
~
Op-Code
0000001
0000
0 0
1
0
A16
A3
A1A2
A0
17-bit Address
MSB LSB
D0
D1
D2
D3
D4
D5
D6
D7
HI-Z
Figure 12. Burst Mode Read Instruction Timing
CS
SCK
SO
LSB
SI
Op-Code
17-bit Address
MSB
LSB
~
~
~
~
~
~
01 2 3 456 7
0
765432
1
20 21 22 23
01234567 01234567
~
~
0
7
0000 00
11 0 0 00 00 0
A16
A3 A2 A1 A0
D0
D1
D2D3
D4
D5
D6
D7
Data Byte 1
Data Byte N
MSB
LSB
MSB
D0
D1
D2D3
D4
D5
D6
D7
D0D7
HI-Z