Datasheet

Document Number: 001-15271 Rev. *E Revised August 25, 2009 Page 24 of 24
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
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CY7C1318JV18
CY7C1320JV18
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Document History Page
Document Title: CY7C1318JV18/CY7C1320JV18, 18 Mbit DDR II SRAM Two Word Burst Architecture
Document Number: 001-15271
Revision ECN
Orig. of
Change
Submission
Date
Description of Change
** 1103944 VKN/KKVTMP See ECN New datasheet
*A 1423243 VKN/AESA See ECN Converted from preliminary to final
Removed 250 MHz and 200 MHz
Updated I
DD
/I
SB
specs
Changed DLL minimum operating frequency from 80 MHz to 120 MHz
Changed t
CYC
max spec to 8.4 ns
*B 2189567 VKN/AESA See ECN Minor Change-Moved to the external web
*C 2521690 NXR/PYRS 06/26/08 Added 250 MHz speed bin
Changed JTAG ID [31:29] from 001 to 000
Updated power up sequence waveform and its description
Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to
“–55°C to +125°C” in the “Maximum Ratings“ on page 20
Added footnote #19 related to I
DD
Changed Θ
JA
and Θ
JC
from 28.51 and 5.91 °C/W to 18.7 and 4.5 °C/W respec-
tively
*D 2561974 VKN/PYRS 09/04/08 Corrected typo in the CY7C1318JV18’s pinout
*E 2755901 VKN 08/25/09 Removed x8 and x9 part number details
Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are available and
modified the disclaimer for the Ordering information.
Updated Package Diagram.
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