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18 Mbit DDR II SRAM Two Word Burst

Architecture

CY7C1318JV18

CY7C1320JV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-15271 Rev. *E Revised August 25, 2009

Features

■ 18 Mbit Density (1M x 18, 512K x 36)

■ 300 MHz Clock for High Bandwidth

■ Two word Burst for reducing Address Bus Frequency

■ Double Data Rate (DDR) Interfaces

(data transferred at 600 MHz) at 300 MHz

■ Two Input Clocks (K and K) for Precise DDR Timing

❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to Minimize Clock

Skew and Flight Time mismatches

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

systems

■ Synchronous Internally self timed Writes

■ DDR II Operates with 1.5 Cycle Read Latency when the DLL

is enabled

■ Operates similar to a DDR I Device with 1 Cycle Read Latency

in DLL Off Mode

■ 1.8V Core Power Supply with HSTL Inputs and Outputs

■ Variable drive HSTL Output Buffers

■ Expanded HSTL Output Voltage (1.4V–V

)

■ Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 Compatible Test Access Port

■ Delay Lock Loop (DLL) for Accurate Data Placement

Configurations

CY7C1318JV18 – 1M x 18

CY7C1320JV18 – 512K x 36

Functional Description

The CY7C1318JV18, and CY7C1320JV18 are 1.8V

Synchronous Pipelined SRAMs equipped with DDR II archi-

tecture. The DDR II consists of an SRAM core with advanced

synchronous peripheral circuitry and a one bit burst counter.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K

. Read data is driven on the rising edges

of C and C

if provided, or on the rising edge of K and K if C/C are

not provided. For CY7C1318JV18 and CY7C1320JV18, the

burst counter takes in the least significant bit of the external

address and bursts two 18 bit words (in the case of

CY7C1318JV18) of two 36 bit words (in the case of

CY7C1320JV18) sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs, D) are tightly matched to the two

output echo clocks CQ/CQ

, eliminating the need to capture data

separately from each individual DDR SRAM in the system

design. Output data clocks (C/C

) enable maximum system

clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self timed write circuitry.

Selection Guide

Description 300 MHz 250 MHz Unit

Maximum Operating Frequency 300 250 MHz

Maximum Operating Current x18 655 600 mA

x36 730 635

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Summary of content (24 pages)

PAGE 1
CY7C1318JV18 CY7C1320JV18 18 Mbit DDR II SRAM Two Word Burst Architecture Features Functional Description ■ 18 Mbit Density (1M x 18, 512K x 36) ■ 300 MHz Clock for High Bandwidth ■ Two word Burst for reducing Address Bus Frequency ■ Double Data Rate (DDR) Interfaces (data transferred at 600 MHz) at 300 MHz ■ Two Input Clocks (K and K) for Precise DDR Timing ❐ SRAM uses rising edges only ■ Two Input Clocks for Output Data (C and C) to Minimize Clock Skew and Flight Time mismatches ■ Echo Clo
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CY7C1318JV18 CY7C1320JV18 Logic Block Diagram (CY7C1318JV18) A(19:1) LD Address Register K CLK Gen. K Write Add. Decode 19 DOFF Write Reg Write Reg 512K x 18 Array 20 512K x 18 Array A(19:0) Read Add. Decode Burst Logic A0 18 Output Logic Control R/W C Read Data Reg. C CQ 36 VREF 18 Control Logic R/W Reg. 18 Reg. 18 CQ 18 18 BWS[1:0] Reg. DQ[17:0] Logic Block Diagram (CY7C1318JV18) A(18:1) LD Address Register K K CLK Gen.
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CY7C1318JV18 CY7C1320JV18 Pin Configuration The pin configuration for CY7C1318JV18, and CY7C1320JV18 follows. [1] 165-Ball FBGA (13 x 15 x 1.
PAGE 4
CY7C1318JV18 CY7C1320JV18 Pin Definitions Pin Name IO Pin Description DQ[x:0] Input OutputSynchronous Data Input Output Signals. Sampled on the rising edge of K and K clocks during valid write operations. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the C and C clocks during read operations or K and K when in single clock mode. When read access is deselected, Q[x:0] are automatically tri-stated.
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CY7C1318JV18 CY7C1320JV18 Pin Definitions Pin Name (continued) IO Pin Description DOFF Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this pin is connected to a pull up through a 10 Kohm or less pull up resistor. The device behaves in DDR I mode when the DLL is turned off.
PAGE 6
CY7C1318JV18 CY7C1320JV18 Functional Overview The CY7C1318JV18, and CY7C1320JV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS the device behaves in DDR I mode with a read latency of one clock cycle. Accesses are initiated on the rising edge of the positive input clock (K).
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CY7C1318JV18 CY7C1320JV18 range of RQ to guarantee impedance matching with a tolerance of ±15 percent is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles at power up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the DDR II to simplify data capture on high speed systems. Two echo clocks are generated by the DDR II. CQ is referenced with respect to C and CQ is referenced with respect to C.
PAGE 8
CY7C1318JV18 CY7C1320JV18 Truth Table The truth table for the CY7C1318JV18, and CY7C1320JV18 follows. [2, 3, 4, 5, 6, 7] Operation K LD R/W Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. L-H L L D(A1) at K(t + 1) ↑ D(A2) at K(t + 1) ↑ Read Cycle: Load address; wait one and a half cycle; read data on consecutive C and C rising edges.
PAGE 9
CY7C1318JV18 CY7C1320JV18 Write Cycle Descriptions The write cycle description table for CY7C1320JV18 follows. [2, 8] BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L–H – During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L H H H L–H L H H H – H L H H L–H H L H H – H H L H L–H H H L H – H H H L L–H H H H L – H H H H L–H H H H H – Document Number: 001-15271 Rev.
PAGE 10
CY7C1318JV18 CY7C1320JV18 IEEE 1149.1 Serial Boundary Scan (JTAG) Instruction Register These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard 1149.1-2001. The TAP operates using JEDEC standard 1.8V IO logic levels. Three bit instructions are serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in on page 13.
PAGE 11
CY7C1318JV18 CY7C1320JV18 device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is given a Test-Logic-Reset state. The shifting of data for the SAMPLE and PRELOAD phases occurs concurrently when required, that is, while the data captured is shifted out, the preloaded data is shifted in.
PAGE 12
CY7C1318JV18 CY7C1320JV18 TAP Controller State Diagram The state diagram for the TAP controller follows. [9] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 1 1 SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 1 0 PAUSE-DR 0 PAUSE-IR 1 0 1 0 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 0 0 1 0 Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-15271 Rev.
PAGE 13
CY7C1318JV18 CY7C1320JV18 TAP Controller Block Diagram 0 Bypass Register 2 Selection Circuitry TDI 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 1 0 1 0 TDO Identification Register 106 . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range [10, 11, 12] Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH Voltage IOH = −2.0 mA 1.4 V VOH2 Output HIGH Voltage IOH = −100 μA 1.
PAGE 14
CY7C1318JV18 CY7C1320JV18 TAP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit 20 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency 50 ns tTH TCK Clock HIGH 20 ns tTL TCK Clock LOW 20 ns tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns Setup Times Hold Times tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Ho
PAGE 15
CY7C1318JV18 CY7C1320JV18 Identification Register Definitions Value Instruction Field Description CY7C1318JV18 CY7C1320JV18 000 000 Cypress Device ID (28:12) 11010100010010101 11010100010100101 Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor. ID Register Presence (0) 1 1 Indicates the presence of an ID register. Revision Number (31:29) Version number. Defines the type of SRAM.
PAGE 16
CY7C1318JV18 CY7C1320JV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 2J 1 6P 29 9G 57 5B 85 3K 2 6N 30 11F 58 5A 86 3J 3 7P 31 11G 59 4A 87 2K 4 7N 32 9F 60 5C 88 1K 5 7R 33 10F 61 4B 89 2L 6 8R 34 11E 62 3A 90 3L 7 8P 35 10E 63 1H 91 1M 8 9R 36 10D 64 1A 92 1L 9 11P 37 9E 65 2B 93 3N 10 10P 38 10C 66 3B 94 3M 11 10N 39 11D 67 1C 95 1N 12 9P 40 9C
PAGE 17
CY7C1318JV18 CY7C1320JV18 Power Up Sequence in DDR II SRAM Power up and initialize QDR-II SRAMs in a predefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW (all other inputs are HIGH or LOW). ❐ Apply VDD before VDDQ. ❐ Apply VDDQ before VREF or at the same time as VREF. ❐ Drive DOFF HIGH. ■ Provide stable DOFF (HIGH) power and clock (K, K) for 1024 cycles to lock the DLL. DLL Constraints ■ DLL uses K clock as its synchronizing input.
PAGE 18
CY7C1318JV18 CY7C1320JV18 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Neutron Soft Error Immunity Parameter Description Ambient Temperature with Power Applied.. –55°C to +125°C Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V DC Input Voltage [11] .............................. –0.5V to VDD + 0.
PAGE 19
CY7C1318JV18 CY7C1320JV18 Electrical Characteristics (continued) DC Electrical Characteristics Over the Operating Range [12] Parameter Description Test Conditions Min Typ Max Unit (x18) 230 mA (x36) 295 (x18) 230 (x36) 295 Notes 15. Power up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 16. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω. 17. Outputs are impedance controlled.
PAGE 20
CY7C1318JV18 CY7C1320JV18 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V Unit CIN Input Capacitance 5 pF CCLK Clock Input Capacitance 6 pF CO Output Capacitance 7 pF 165 FBGA Package Unit 18.7 °C/W 4.5 °C/W Thermal Resistance Tested initially and after any design or process change that may affect these parameters.
PAGE 21
CY7C1318JV18 CY7C1320JV18 Switching Characteristics Over the Operating Range [20, 21] Cypress Consortium Parameter Parameter 300 MHz Description 250 MHz Min Max Min Max VDD(Typical) to the first Access [22] Unit 1 – 1 – ms tCYC tKHKH K Clock and C Clock Cycle Time 3.30 8.4 4.0 8.4 ns tKH tKHKL Input Clock (K/K and C/C) HIGH 1.32 – 1.6 – ns tKL tKLKH Input Clock (K/K and C/C) LOW 1.32 – 1.
PAGE 22
CY7C1318JV18 CY7C1320JV18 Switching Waveforms Figure 5. Read/Write/Deselect Sequence [26, 27, 28] READ 2 NOP 1 READ 3 NOP 4 NOP 5 WRITE 6 WRITE 7 READ 8 A3 A4 9 10 K tKH tKL tKHKH tCYC K LD tSC tHC R/W A A0 tSA A2 A1 tHD tHA tHD tSD DQ Q00 t KHCH t CLZ Q01 Q10 Q11 tSD D20 D21 D30 D31 Q40 Q41 t CQDOH t CHZ tDOH tCO t CQD C t KHCH tKH tKL tCYC tKHKH C# tCQOH tCCQO CQ tCQOH tCCQO tCQH tCQHCQH CQ# DON’T CARE UNDEFINED Notes 26.
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CY7C1318JV18 CY7C1320JV18 Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors.
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CY7C1318JV18 CY7C1320JV18 Document History Page Document Title: CY7C1318JV18/CY7C1320JV18, 18 Mbit DDR II SRAM Two Word Burst Architecture Document Number: 001-15271 Revision ECN Orig. of Change Submission Description of Change Date ** 1103944 VKN/KKVTMP See ECN New datasheet *A 1423243 VKN/AESA See ECN Converted from preliminary to final Removed 250 MHz and 200 MHz Updated IDD/ISB specs Changed DLL minimum operating frequency from 80 MHz to 120 MHz Changed tCYC max spec to 8.