User`s manual

X5-GSPS XMC Module
Performance Data
Power Consumption
The X5-GSPS requires the following power for typical operation with when using the FrameWork Logic. This typical
number assumes a 250 MHz system clock rate and 125 MSPS A/D and D/A data rates for the application logic.
Table 17. X5-GSPS Power Consumption
Voltage Maximum Allowed
Current (A)
Typical Current
Required (A)
Typical
Power (W)
Derived from Supplies these Devices
3.3V 15 5.1A 16.8 Direct connect to the
PCIe host
FPGA, clock controls, and
analog power supplies
12V 4 0.83 9.96 Direct connect to the
PCIe host (VPWR
pins)
FPGA
Total
Power
26.8
Surge currents occur initially at power-on and after application logic initialization. The power-on surge current lasts for
about 10 ms at several amperes on both 3.3V and 12V. This surge is due primarily to charging the on-card capacitors and the
startup current of the FPGAs. After initial power-up, the logic configuration will also result in a step change to the current
consumption because the logic will begin to operate. In our testing and measurements, this has not been a surge current as
much as a just a step change in the power consumption.
Power consumption varies and is primarily as a function of the logic design. Logic designs with high utilization and fast
clock rates require higher power. Since calculating power consumption in the logic requires many details to be considered,
Xilinx tools such as XPower are used to get the best estimates.
It is important that any custom logic design have a substantial safety margin for the power consumption. Allowance for
decreased power supply efficiency due to heating can account for 10% derating. Also, dynamic loads should be considered so
that peak power is adequate. In many cases a factor of 2 for derating is recommended.
X5-GSPS User's Manual 89