User`s manual

List of Figures
Figure 1. Innovative Install Program...................................................................................................15
Figure 2. Progress is shown for each section........................................................................................16
Figure 3. ToolSet registration form.......................................................................................................17
Figure 4. BusMaster configuration.......................................................................................................17
Figure 5. Installation complete..............................................................................................................17
Figure 6. Innovative Single lane PCIe – XMC.3 adapter card (P/N 80172).........................................24
Figure 7. Innovative PCI 64/66 – XMC.3 (4x lanes) adapter card (P/N 80167-0).............................25
Figure 8. Innovative x8 Lane PCI Express – XMC.3 (8x lanes) adapter card (P/N 80173-0)...........25
Figure 9. eInstrument Node – cabled PCI Express adapter (x1 lane) for XMC Modules (II P/N 90181)
...............................................................................................................................................................25
Figure 10. eInstrument PC – embedded PC (Windows/Linux) hosts two XMC modules (II P/N
90199)...................................................................................................................................................26
Figure 11. X5 XMC Family Block Diagram.........................................................................................28
Figure 12. DIO Control Register (BAR1+0x14)...................................................................................34
Figure 13. Digital IO Port Addresses....................................................................................................34
Figure 14. Virtex-5 Rocket I/O assignments for P16 signals................................................................37
Figure 15. XMC EEProm Programmer.................................................................................................41
Figure 16. X5-GSPS Module (analog cover and heat sink removed)...................................................75
Figure 17. X5-GSPS Block Diagram....................................................................................................76
Figure 18. X5-GSPS A/D Channel 0 Front End...................................................................................78
Figure 19. X5-GSPS A/D Channel 1 Front End...................................................................................78
Figure 20. Sample Clock Generation and Distribution Block Diagram...............................................79
Figure 21. Input Clock Electrical Specifications..................................................................................80
Figure 22. Clock Oscillator Electrical Specifications...........................................................................80
Figure 23. Analog Triggering Timing...................................................................................................82
Figure 24. X5-GSPS FrameWork Logic Data Flow.............................................................................83
Figure 25. Frequency Response for 10 MHz to 1 GHz span, 500 mVp-p input...................................91
Figure 26. Frequency Response for 600 MHz to 900 MHz span, 500 mVp-p input............................91
Figure 27. X5-GSPS Ground Noise, Fs = 125 MSPS, input grounded................................................92
Figure 28. X5-GSPS Noise Floor, Fs = 125 MSPS, input grounded....................................................92
Figure 29. X5-GSPS A/D Signal Quality vs. Input Amplitude.............................................................93
Figure 30. Signal Quality vs Input Frequency, Fin = 101 MHz, 2 Vp-p...............................................94
Figure 1. Signal Quality, Fin = 101 MHz, 2Vp-p, Fs = 1497.5 MSPS, DC Coupled...........................95
Figure 2. Signal Quality, Fin = 101 MHz, 2Vp-p, Fs = 1497.5 MSPS, DC Coupled...........................96
Figure 3. Signal Quality, Fin = 101 MHz, 2Vp-p, Fs = 637.5 MSPS, DC Coupled.............................97
Figure 4. Connectors J1-J4 Functions...................................................................................................98
Figure 5. P15 XMC Connector Orientation..........................................................................................99
Figure 6. P16 XMC Connector Orientation........................................................................................102
Figure 7. X5-GSPS JP1 Orientation, board face view........................................................................105
Figure 8. X5-GSPS JP1 Orientation, board top edge view.................................................................105
Figure 9. X5-GSPS Mechanicals (Top View) Rev A..........................................................................107
Figure 10. X5-GSPS Mechanicals (Bottom View) Rev A..................................................................108