User`s manual

List of Tables
Table 1. X5 XMC Bus Requirements....................................................................................................23
Table 2. Required PCIe Resource Allocations......................................................................................26
Table 3. XMC Mounting Hardware......................................................................................................27
Table 4. X5 XMC Family......................................................................................................................28
Table 5. X5 XMC Family Peripherals...................................................................................................29
Table 6. X5 Computing Core Devices..................................................................................................30
Table 7. PCI Express Standards Compliance........................................................................................31
Table 8. Interfaces from PCI Express to Application Logic.................................................................31
Table 9. IUsesDioPort Class Operations...............................................................................................33
Table 10. Digital IO Bits Electrical Characteristics..............................................................................35
Table 11. X5 JTAG Scan Path...............................................................................................................39
Table 12. Development Tools for the Windows Snap Example............................................................43
Table 13. X5-GSPS A/D Features.........................................................................................................77
Table 14. A/D Conversion Coding........................................................................................................78
Table 15. Alert Types.............................................................................................................................85
Table 16. Alert Packet Format...............................................................................................................86
Table 17. X5-GSPS Power Consumption.............................................................................................89
Table 18. X5-GSPS Environmental Limits...........................................................................................89
Table 19. X5-GSPS Analog Performance Summary.............................................................................90
Table 20. X5-GSPS XMC Connector P15 Pinout...............................................................................100
Table 21. P15 Signal Descriptions......................................................................................................101
Table 22. X5-GSPS XMC Secondary Connector P16 Pinout.............................................................103
Table 23. P16 Signal Descriptions......................................................................................................104
Table 24. X5-GSPS JP3 Xilinx JTAG Connector Pinout....................................................................106