User`s manual

About the X5 XMC Modules
P16 Signal Virtex-5 FG1136 Pin Number Virtex-5 MGT Signal Identifier
TXN4 L2 MGT_116_TXP1
RXP4 J1 MGT_116_RXN1
RXN4 K1 MGT_116_RXP1
TXP5 G2 MGT_116_ TXN0
TXN5 F2 MGT_116_TXP0
RXP5 H1 MGT_116_RXN0
RXN5 G1 MGT_116_RXP0
TXP6 AN9 MGT_126_ TXN1
TXN6 AN10 MGT_126_TXP1
RXP6 AP8 MGT_126_RXN1
RXN6 AP9 MGT_126_RXP1
TXP7 AN6 MGT_126_ TXN0
TXN7 AN5 MGT_126_TXP0
RXP7 AP7 MGT_126_RXN0
RXN7 AP6 MGT_126_RXP0
Figure 15. Virtex-5 Rocket I/O assignments for P16 signals
Note that the positive and negative polarities of the individual lanes are reversed between the polarity notation on the P16
connector versus the polarity notation on the Rocket I/O pin pairs. This was done to avoid vias on the PC board and thus
optimize the layout for signal integrity purposes. If needed by the application , strict signal polarity can be reversed in the
Virtex-5 logic design by using the Rocket I/O polarity controls within each MGT tile.
Reference clocks running at 125 MHz are connected to the reference clock input pins of MGT_126 and MGT_120 (pins AL7,
AM7, E4, and D4 respectively). This clock is supplied by an LVPECL oscillator at location Y3. If a different frequency is
required by the user's application, this oscillator can be replaced by any 6 pin 2.5V LVPECL output device compatible with
Pletronics LV7745DEW footprint.
Thermal Protection and Monitoring
The Virtex-5 logic device includes a temperature and voltage monitoring subsystem called System Monitor. The X5 design
uses the System Monitor to check Virtex-5 device die temperature and control the enable/disable feature on key board power
supplies. This allows logic to disable power on the card in the event of an over-temperature condition within the Virtex-5
device. In the event of an over-temperature condition, the logic, memory interface, and analog power supplies are disabled,
X5-GSPS User's Manual 39