User`s manual

About the X5 XMC Modules
Since the bit I/O is not connected to the high speed data stream, this limits the effective update or read rate to about 1 MHz.
Custom logic implementations can achieve much higher data rates by creating logic for data packets transfers to the Digital
IO.
The X5 FrameWork Logic user Guide details logic supporting the digital IO port and gives the pin information for
customization.
P16 SERDES I/O
The X5 series implements a high speed SERDES communication system on the XMC P16 connector to allow data to be
exchanged with the host outside of the PCI Express bus. P16 connections on the X5 are compatible with the VITA 42.0
secondary connector specification, and provide eight transmit and receive pairs implemented using Virtex-5 Rocket I/O links.
A clock reference is provided on board for use by the Rocket I/O links.
Pinouts for the P16 connector showing the transmit and receive pair locations are given in the Connectors section. The
following table gives the Rocket I/O pin allocations on the Virtex-5 which connect to each of the P16 signals.
P16 Signal Virtex-5 FG1136 Pin Number Virtex-5 MGT Signal Identifier
TXP0 B6 MGT_124_ TXN1
TXN0 B5 MGT_124_TXP1
RXP0 A7 MGT_124_RXN1
RXN0 A6 MGT_124_RXP1
TXP1 B9 MGT_124_ TXN0
TXN1 B10 MGT_124_TXP0
RXP1 A8 MGT_124_RXN0
RXN1 A9 MGT_124_RXP0
TXP2 D2 MGT_120_ TXN1
TXN2 E2 MGT_120_TXP1
RXP2 C1 MGT_120_RXN1
RXN2 D1 MGT_124_RXP1
TXP3 B3 MGT_120_ TXN0
TXN3 B4 MGT_120_TXP0
RXP3 A2 MGT_120_RXN0
RXN3 A3 MGT_124_RXP0
TXP4 K2 MGT_116_ TXN1
X5-GSPS User's Manual 38