User`s manual
About the X5 XMC Modules
Data
may
be
written
to/read
from
the
digital
I/O
port
using
the
digital
I/O
port
data
registers.
Data
written to
ports
bits
which
are
set
for
output
mode
will
be
latched
and
driven
to
the
corresponding
port
pins, while
data
written
to
input
bits
will
be
ignored.
The
input
DIO
may
be
clocked
externally
by
enabling the
external
digital
clock
bit
in
the
appropriate
configuration
register.
If
the
internal
clock
is
used,
the data
is
latched
at
the
beginning
of
any
read
from
the
port.
Data
read
from
output
bits
is
equal
to
the
last latched
bit
values
(i.e.
the
last
data
written
to
the
port
by
the
host ).
Digital
I/O
port
pins
are
set to all inputs after logic configuration
.
External
signals
connected
to
the
digital
I/O
port
bits
or
timer
input
pins
should
be
limited
to
a
voltage range
between
0
and
3.3V
referenced
to
ground
on
the
digital
I/O
port
connector.
Exceeding
these
limits will
cause
damage
to
the
X5 hardware.
Digital
IO
Electrical
Characteristics
The
digital
IO
pins
are
LV
TTL
compatible pins
driven
by
3.3V
logic.
The DIO port pins connect to the application FPGA via
100 ohm series resistors.
Warning
: the DIO pins are
NOT
5V compatible. Input voltage must not exceed 4.05V during normal operation. Undershoot
and overshoot must be limited: see the Xilinx Virtex-5 User Guide for details.
Parameter Value Notes
Input Voltage Max = 4.05V
Min = -0.75V
Exceeding these will damage
the FPGA
Output Voltage ''1' > 2.4V
'0' < 0.4V
For load < +/-12mA
Output Current +/-12mA FPGA can be reconfigured for
custom designs for other drive
currents.
Input Logic
Thresholds
'1' >= 2VDC
'0' < 0.8VDC
Input Impedance >1M ohm || 15 pF Excludes cabling
Table 10. Digital IO Bits Electrical Characteristics
Notes on Digital IO Use
The digital I/O on X5 modules, as supported using the standard FrameWork Logic, is intended for low speed bit I/O controls
and status. The interface is capable of data rates exceeding 75 MHz and custom logic developers can implement much higher
speed and sophisticated interfaces by modifying the logic.
X5-GSPS User's Manual 37