User`s manual

About the X5 XMC Modules
The SRAM devices connected to the FPGA are 4 Mbytes total size, organized as two banks of 16Mbitx32 dual ported
memory. This device is an Cypress CY7C1314 (or equivalent) which is a synchronous QDR2 SRAM and supports clock rates
up to 167 MHz. All SRAM control and data lines pins are directly connected to the FPGA, allowing the SRAM memory
control to be customized to the application.
The Framework Logic provides a simple SRAM interface that can be readily modified for many types of applications.
Detailed explanation of the interface control logic is described in the FrameWork Logic User Guide. The Framework Logic
provides a simple register interface to the SBSRAM control logic that is used for test and demonstration. FPGA logic
developers can easily replace the simple register interface logic to build on top of the high performance logic core when
integrating the SRAM into their logic design.
MATLAB developers frequently use the SRAM as the real-time data buffer during development. Since the MATLAB
Simulink tools operate over the FPGA JTAG during development at a low rate, it is necessary to use the SRAM for real-time,
high speed data buffering. The MATLAB Simulink library for each X5 module demonstrates the use of the SRAM as a data
capture buffer. The SRAM captures real-time, high-speed data that can then be read out into MATLAB for analysis or display
as a snapshot. This allows high-speed, real-time to be captured and brought into MATLAB Simulink over the slow
(10Mb/sec) JTAG link. See the X5 FrameWork Logic User Guide for more details and examples.
Data Buffer DRAM
The second set of memory provides a 512MByte DDR2 memory pool local to the FPGA. The Framework Logic implements
a data buffer with one or more queues for the A/D and D/A streams as appropriate for the particular X5 module.
In the Framework logic, the SRAM use is demonstrated as a multiple queue FIFO memory that divides the 2 MB memory
buffer into separate queues (virtual FIFOs) for input and output. The logic component, referred to as Multi-Queue DRAM,
controls the DRAM to create the FIFO queue functionality. Custom logic applications can use the Multi Queue DRAM
buffer component to add additional queues for new devices.
Serial EEPROM Interface
EEPROM
A serial EEPROM on the X5 series is used to store configuration and calibration information. The interface to the serial
EEPROM is an I2C bus that is controlled by the PCI logic device. The device is an Atmel AT24C16-10SI, a 16K bit device.
The I2C bus is slow and the calibration is read out of the EEPROM at initialization time by the application software and
written into registers in the application logic for real-time error correction.
The EEPROM also has a write cycle limit of 100K cycles, so it should only be written to when calibration is performed or
configuration information changes. Once the write cycle duration limit is exceeded, the device will not reliably store data any
more.
As delivered from the factory, this EEPROM contains the calibration coefficients used for the A/D and D/A error correction.
Caution: the serial EEPROM contains the calibration coefficients for the analog and is preprogrammed at factory test. Do
not erase these coefficients or calibration will be lost.
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