User`s manual

About the X5 XMC Modules
Table 7. PCI Express Standards Compliance
Standard Describes Standards Group
PCI Express 1.0a PCI Express electrical and protocol standards.
2.5 Gbps data rate per lane per direction.
PCI SIG ( http://www.picmg.com )
ANSI/VITA 42 XMC module mechanicals and connectors VITA ( www.vita.org )
ANSI VITA 42.3 XMC module with PCI Express Interface. VITA ( www.vita.org )
The major interfaces to the application logic are the data link, command channel and SelectMAP interface. The data link
provides a high performance channel for the application logic to communicate with the host computer while the Command
Channel is a command and control interface from the host computer to the application logic. The SelectMAP interface is the
application FPGA configuration port for loading the logic image.
The data link is the primary data path for the data communications between the application FPGA and host computer. When
data packets are created by the application logic, such as A/D samples, or required by the application logic for output devices,
such as DAC channels, the data flows over the data link as packets. The maximum transfer rate over the data link is 2000
MB/s with a 1200 MB/s sustained rate (half-duplex). The data packets contain a Peripheral Device Number (PDN) that
identifies the peripheral associated with the this data packet. In this way, the packet system is extensible to other devices that
may be added to the logic. For example, an FFT analysis can be added to the logic and its result sent to the host as a new
PDN for display and further analysis while maintaining other data streams from A/D channels.
Table 8. Interfaces from PCI Express to Application Logic
Application Logic
Interface
Max Data Rate Typical Use
Data Link 2000 MB/s burst, 1200 MB/s sustained
(half-duplex)
Velocia packet system interface -
main path for data communications
Command Channel 5 MB/s sustained Command, control and status
Data Buffering and Memory Use
There are two sets of memory devices attached to the application FPGA that provide data buffering and computational RAM
for FPGA applications.
Computational SRAM
The SRAM on the X5 series is a 4Mbyte memory dedicated as FPGA local memory. Applications in the FPGA may use the
SRAM as a local buffer memory if the data buffer is too large to fit in FPGA block RAMs, or as memory for an embedded
processor in the FPGA.
X5-GSPS User's Manual 33