User`s manual

About the X5 XMC Modules
Table 6. X5 Computing Core Devices
Feature Device Part Number
Application Logic FPGA Xilinx Virtex-5 SX95T XC5VSX95T-1FFG1136C
Computation memory QDR2 SRAM 2x Cypress CY7C1314BV18-167
Buffer memory DDR2 DRAM 4x Micron MT47H64M16HR-37E
As the focus of the module, the X5 computing core connects the IO, peripherals, host communications and support features.
Each IO device directly connects to the application FPGA on the X5 modules providing tight coupling for high performance,
real-time IO. The FPGA logic implements an interface to each device that connects them to the controls and data
communications features on the module. Support features, such as sample triggering and data analysis, are implemented in
the logic to provide precise real-time control over the data acquisition process.
The X5 module architecture is really defined by the features in the logic that connect the IO devices to Velocia packet system.
For data from IO devices such as A/Ds, the data flows from the IO interface and is then enqueued in the multi-queue buffer.
The packetizer then creates data packets from the data stream that are moved across the data link to the PCIe interface.
Packets to output devices travel in the opposite direction – from the link to the de-framer and into the multi-queue data buffer.
The output IO, such as a DAC, then consumes the data from the queue as required. The Alert Log monitors error conditions
and important events for management of the data acquisition process.
The host interacts with the X5 computing core using the packet system for high speed data and over the command channel.
The packet system is the main data channel to the card and delivers the high performance, real-time data capability of moving
data to and from the module. Since it uses an efficient DMA system, it is very efficient at moving data which leaves the host
system unburdened by the data flow. The command channel provides the PCIe host direct access to the computing core logic
for status, control and initialization. Since it is outside the packet system, it is less complex to use and provides unimpeded
access to the logic.
The application FPGA image is loaded at power up from onboard flash EEPROM storage.
Adding New Features to the FPGA
The functionality of the computing core can be modified using the FrameWork Logic tools for the X5 module family. The
tools support development in either VHDL or MATLAB. Signal processing, data analysis and unique functions can be added
to the X5 modules to suit application-specific requirements. See the X5 FrameWork Logic User Guide for further
information.
X5 PCI Express Interface
The X5 module family has a PCI Express interface that provides a lane, 2.5 Gbps full duplex link to the host computer. The
interface is compatible with industry standard PCI Express systems and may be used in a variety of host computers. The
following standards govern the PCI Express interface on the X5 XMC modules.
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