User`s manual

About the X5 XMC Modules
X5 XMC Features Applications
500M updates/sec
X5-210M 4 A/D channels, 14 bit, 250 MHz Software radio, RADAR
X5-GSPS 2 A/D channels at 1.5GSPS IF/RF simulation and test, RADAR
X5-COM 4 SFP ports at 3.125 Gbps Remote IO, system expansion
The X5 XMCs feature a Xilinx Virtex-5 SX95T core for signal processing and control. In addition to the features in the
Virtex-5 logic such as embedded multipliers and memory blocks, the FPGA computing core has one bank of DDR2 DRAM
and two banks of QDR2 SRAM for data buffering and computing memory.
There are also a number of support peripherals for IO control and system integration. Each XMC may have additional
application-specific support peripherals.
Table 5. X5 XMC Family Peripherals
Peripheral Features
XMC.3 PCI Express
interface
The XMC.3 host interface integrates with PCI Express systems using eight lanes operating at 2.5 Gbps
that provides up to 4 GBytes/sec data rate on the bus (full duplex). This interface complies with VITA
standard 42.3 which specifies PCI Express interface for the XMC module format.
The Velocia packet system provides fast and flexible communications with the host using a credit-based
flow control supporting packet transfers with the host. A secondary command channel provides
independent interface for control and status outside of the data channel that is extensible to custom
applications.
XMC P16 Provides a bank of digital IO lines which may be used for general purpose bit I/O or to implement a
private link to cards featuring a parallel data bus. Additionally, eight independent rocket I/O links
(VITA 42.0) are available, each capable of 500 MB/s, full-duplex operation
Timing and triggering Flexible clocking and synchronization features for I/O
Data buffering and
Computational Memory
Two 1Mx16 SRAM devices are used provide data buffering, processor memory and computation
memory for the Application FPGA
Alert Log Monitors system events and error conditions to help manage the data acqusiton process
X5 Computing Core
The X5 XMC module family has an FPGA-based computing core that controls the data acquisition process, provides data
buffing and host communications. The computing core consists of a Xilinx Virtex-5 FPGA, one bank of DDR2 DRAM
(4Gbits in a x64 configuration), and two banks of QDR2 SRAM (32Mbits total in two x32 dual-ported banks). The FPGA
uses the memories for data buffering and computational workspace.
X5-GSPS User's Manual 31