Datasheet

CY7C1312BV18
CY7C1314BV18
Document #: 38-05619 Rev. *G Page 7 of 27
Echo Clocks
Echo clocks are provided on the QDR II to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C
. These are free-running clocks and are
synchronized to the output clock (C/C) of the QDR II. In single
clock mode, CQ is generated with respect to K and CQ
is
generated with respect to K. The timing for the echo clocks is
shown in the Switching Characteristics on page 21.
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
DLL is locked after 1024 cycles of stable clock. The DLL can also
be reset by slowing or stopping the input clock K and K
for a
minimum of 30 ns. However, it is not necessary to reset the DLL
to lock to the desired frequency. The DLL automatically locks
1024 clock cycles after a stable clock is presented. The DLL may
be disabled by applying ground to the DOFF pin. For information
refer to the application note AN5062, DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+.
Application Example
Figure 1 shows two QDR II used in an application.
Figure 1. Application Example
R = 250ohms
Vt
R
R = 250ohms
Vt
Vt
R
Vt = Vddq/2
R = 50ohms
R
CC#
D
A
SRAM #2
R
P
S
#
W
P
S
#
B
W
S
#
ZQ
CQ/CQ#
Q
K#
CC#
D
A
K
SRAM #1
R
P
S
#
W
P
S
#
B
W
S
#
ZQ
CQ/CQ#
Q
K#
BUS
MASTER
(CPU
or
ASIC)
DATA IN
DATA OUT
Address
RPS#
WPS#
BWS#
Source K
Source K#
Delayed K
Delayed K#
CLKIN/CLKIN#
K
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