Datasheet

CY7C1292DV18
CY7C1294DV18
Document #: 001-00350 Rev. *E Page 8 of 26
with respect to C. These are free-running clocks and are
synchronized to the output clock (C/C
) of the QDR II. In the single
clock mode, CQ is generated with respect to K and CQ
is
generated with respect to K
. The timings for the echo clocks are
shown in the AC Timing table.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed to
function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF
is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for
a minimum of 30 ns. However, it is not necessary for the DLL to
be specifically reset to lock the DLL to the desired frequency. The
DLL automatically locks 1024 clock cycles after a stable clock is
presented. The DLL may be disabled by applying ground to the
DOFF
pin. For information refer to the application note “DLL
Considerations in QDRII/DDRII/QDRII+/DDRII+”.
Application Example
Figure 1 shows four QDR II used in an application.
Figure 1. Application Example
R = 250ohms
Vt
R
R = 250ohms
Vt
Vt
R
Vt = Vddq/2
R = 50ohms
R
CC#
D
A
SRAM #4
R
P
S
#
W
P
S
#
B
W
S
#
K
ZQ
CQ/CQ#
Q
K#
CC#
D
A
K
SRAM #1
R
P
S
#
W
P
S
#
B
W
S
#
ZQ
CQ/CQ#
Q
K#
BUS
MASTER
(CPU
or
ASIC)
DATA IN
DATA OUT
Address
RPS#
WPS#
BWS#
Source K
Source K#
Delayed K
Delayed K#
CLKIN/CLKIN#