Datasheet

CY7C1292DV18
CY7C1294DV18
Document #: 001-00350 Rev. *E Page 2 of 26
Contents
Features ..............................................................................1
Configurations ....................................................................1
Functional Description .......................................................1
Selection Guide ..................................................................1
Contents ..............................................................................2
Logic Block Diagram (CY7C1292DV18) ............................3
Logic Block Diagram (CY7C1294DV18) ............................3
Pin Configuration ...............................................................4
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout ....................4
Pin Definitions ....................................................................5
Functional Overview ..........................................................7
Read Operations ...........................................................7
Write Operations ...........................................................7
Byte Write Operations ................................................... 7
Single Clock Mode ........................................................7
Concurrent Transactions ...............................................7
Depth Expansion ........................................................... 7
Programmable Impedance ............................................7
Echo Clocks ..................................................................7
DLL ................................................................................8
Application Example ..........................................................8
Truth Table ..........................................................................9
Write Cycle Descriptions ...................................................9
Write Cycle Descriptions .................................................10
IEEE 1149.1 Serial Boundary Scan (JTAG) ....................11
Disabling the JTAG Feature ........................................11
Test Access Port—Test Clock ..................................... 11
Test Mode Select ........................................................11
Test Data-In (TDI) .......................................................11
Test Data-Out (TDO) ...................................................11
Performing a TAP Reset ............................................. 11
TAP Registers ............................................................. 11
TAP Instruction Set ..................................................... 11
TAP Controller State Diagram .........................................13
TAP Controller Block Diagram ........................................14
TAP Electrical Characteristics ........................................ 14
TAP Timing and Test Conditions ....................................15
Identification Register Definitions ..................................16
Scan Register Sizes .........................................................16
Instruction Codes .............................................................16
Boundary Scan Order ......................................................17
Power up Sequence in QDR II SRAM ............................. 18
Power up Sequence .................................................... 18
DLL Constraints ..........................................................18
Maximum Ratings .............................................................19
Operating Range ..............................................................19
Electrical Characteristics ................................................19
DC Electrical Characteristics ....................................... 19
AC Input Requirements ............................................... 20
Capacitance ......................................................................20
Thermal Resistance .........................................................20
Switching Characteristics ...............................................21
Switching Waveforms ......................................................22
Ordering Information .......................................................23
Ordering Code Definition..................................................23
Package Diagram .............................................................23
Document History Page ...................................................24
Sales, Solutions, and Legal Information ........................25
Worldwide Sales and Design Support ......................... 25
Products ...................................................................... 25
PSoC Solutions ........................................................... 25