Datasheet

CY7C1292DV18
CY7C1294DV18
Document #: 001-00350 Rev. *E Page 9 of 26
Truth Table
The truth table for CY7C1292DV18 and CY7C1294DV18 follows.
[3, 4, 5, 6, 7, 8]
Operation K RPS WPS DQ DQ
Write Cycle:
Load address on the rising edge of K
clock; input write
data on K and K
rising edges.
L-H X L D(A + 0) at K(t)  D(A + 1) at K
(t) 
Read Cycle:
Load address on the rising edge of K clock; wait one
and a half cycle; read data on C
and C rising edges.
L-H L X Q(A + 0) at C
(t + 1) Q(A + 1) at C(t + 2) 
NOP: No Operation L-H H H D = X,
Q = High-Z
D = X,
Q = High-Z
Standby: Clock Stopped Stopped X X Previous State Previous State
Write Cycle Descriptions
The write cycle description table for CY7C1292DV18 follows.
[3, 9]
BWS
0
BWS
1
K K Comments
L L L-H – During the data portion of a write sequence both bytes (D
[17:0]
) are written into the device.
L L – L-H During the data portion of a write sequence both bytes (D
[17:0]
) are written into the device.
L H L-H – During the data portion of a write sequence only the lower byte (D
[8:0]
) is written into the device.
D
[17:9]
remains unaltered.
L H – L-H During the data portion of a write sequence only the lower byte (D
[8:0]
) is written into the device.
D
[17:9]
remains unaltered.
H L L-H – During the data portion of a write sequence only the upper byte (D
[17:9]
) is written into the
device. D
[8:0]
remains unaltered.
H L – L-H During the data portion of a write sequence only the upper byte (D
[17:9]
) is written into the
device. D
[8:0]
remains unaltered.
H H L-H – No data is written into the devices during this portion of a write operation.
H H – L-H No data is written into the devices during this portion of a write operation.
Notes
2. The above application shows four QDR II being used.
3. X = “Don't Care,” H = Logic HIGH, L= Logic LOW,
represents rising edge.
4. Device powers up deselected and the outputs in a tristate condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
6. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
7. Data inputs are registered at K and K
rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
8. It is recommended that K = K
and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
9. Assumes a write cycle was initiated per the Write Port Cycle Description Truth Table. BWS
0
, BWS
1
, BWS
2
, and BWS
3
can be altered on different portions of a write
cycle, as long as the setup and hold requirements are achieved.