THIS SPEC IS OBSOLETE Spec No: 001-00350 Spec Title: CY7C1292DV18/CY7C1294DV18 9-Mbit QDR® II SRAM 2-Word Burst Architecture Sunset Owner: AJU Replaced By: None
CY7C1292DV18 CY7C1294DV18 9-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations ■ Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1292DV18 – 512K x 18 CY7C1294DV18 – 256K x 36 ■ 250 MHz clock for high bandwidth Functional Description ■ 2-Word Burst on all accesses ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising ed
CY7C1292DV18 CY7C1294DV18 Contents Features .............................................................................. 1 Configurations .................................................................... 1 Functional Description ....................................................... 1 Selection Guide .................................................................. 1 Contents .............................................................................. 2 Logic Block Diagram (CY7C1292DV18) ..........
CY7C1292DV18 CY7C1294DV18 Logic Block Diagram (CY7C1292DV18) K K CLK Gen. DOFF Address Register Read Add. Decode 18 Write Reg 256K x 18 Array Address Register Write Reg 256K x 18 Array A(17:0) 18 Write Add. Decode D[17:0] 18 RPS Control Logic C C Read Data Reg. 36 VREF WPS Control Logic BWS[1:0] A(17:0) CQ CQ 18 Reg. 18 Reg. 18 18 Reg. Q[17:0] 18 Logic Block Diagram (CY7C1294DV18) DOFF VREF WPS BWS[3:0] CLK Gen. Address Register Read Add.
CY7C1292DV18 CY7C1294DV18 Pin Configuration The pin configuration for CY7C1292DV18 and CY7C1294DV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.
CY7C1292DV18 CY7C1294DV18 Pin Definitions Pin Name I/O Pin Description D[x:0] InputData Input Signals, sampled on the rising edge of K and K clocks during valid write operations. Synchronous CY7C1292DV18 - D[17:0] CY7C1294DV18 - D[35:0] WPS InputWrite Port Select, Active LOW. Sampled on the rising edge of the K clock. When asserted active, Synchronous a write operation is initiated. Deasserting deselects the write port. Deselecting the write port causes D[x:0] to be ignored.
CY7C1292DV18 CY7C1294DV18 Pin Definitions (continued) Pin Name I/O Pin Description DOFF Input DLL Turn Off, Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timings in the DLL turned off operation are different from those listed in this data sheet. TDO Output TCK Input TCK pin for JTAG. TDI Input TDI pin for JTAG. TMS Input TMS pin for JTAG. NC N/A Not connected to the Die. Can be tied to any voltage level. NC/18M N/A Not connected to the Die.
CY7C1292DV18 CY7C1294DV18 Functional Overview The CY7C1292DV18 and CY7C1294DV18 are synchronous pipelined Burst SRAMs equipped with both a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and out through the read port. These devices multiplex the address inputs to minimize the number of address pins required.
CY7C1292DV18 CY7C1294DV18 with respect to C. These are free-running clocks and are synchronized to the output clock (C/C) of the QDR II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. DLL These chips utilize a Delay Lock Loop (DLL) that is designed to function between 80 MHz and the specified maximum clock frequency.
CY7C1292DV18 CY7C1294DV18 Truth Table The truth table for CY7C1292DV18 and CY7C1294DV18 follows. [3, 4, 5, 6, 7, 8] Operation K RPS WPS Write Cycle: Load address on the rising edge of K clock; input write data on K and K rising edges. L-H X L D(A + 0) at K(t) D(A + 1) at K(t) Read Cycle: Load address on the rising edge of K clock; wait one and a half cycle; read data on C and C rising edges.
CY7C1292DV18 CY7C1294DV18 Write Cycle Descriptions The write cycle description table for CY7C1294DV18 follows. [3, 9] BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L-H - During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L L L L - L H H H L-H L H H H - H L H H L-H H L H H - H H L H L-H H H L H - H H H L L-H H H H L - H H H H L-H H H H H - Document #: 001-00350 Rev.
CY7C1292DV18 CY7C1294DV18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-1900. The TAP operates using JEDEC standard 1.8V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device.
CY7C1292DV18 CY7C1294DV18 IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.
CY7C1292DV18 CY7C1294DV18 TAP Controller State Diagram The state diagram for the TAP controller follows. [10] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 Note 10. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 001-00350 Rev.
CY7C1292DV18 CY7C1294DV18 TAP Controller Block Diagram 0 Bypass Register 2 Selection Circuitry TDI 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 1 0 1 0 TDO Identification Register 106 . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range [11, 12, 13] Parameter Description Test Conditions Min. Max. Unit VOH1 Output HIGH Voltage IOH =2.0 mA 1.4 V VOH2 Output HIGH Voltage IOH =100 A 1.
CY7C1292DV18 CY7C1294DV18 TAP AC Switching Characteristics Over the Operating Range [14, 15] Parameter Description Min. Max.
CY7C1292DV18 CY7C1294DV18 Identification Register Definitions Instruction Field Value CY7C1292DV18 CY7C1294DV18 000 000 Cypress Device ID (28:12) 11010011010010110 11010011010100110 Cypress JEDEC ID (11:1) 00000110100 00000110100 ID Register Presence (0) 1 1 Revision Number (31:29) Description Version number. Defines the type of SRAM. Unique identification of SRAM vendor. Indicates the presence of an ID register.
CY7C1292DV18 CY7C1294DV18 Boundary Scan Order Bit # Bump ID Bit # 0 6R 27 1 6P 28 2 6N 29 3 7P 30 4 7N 31 5 7R 6 8R 7 8P Bump ID Bit # Bump ID Bit # Bump ID 11H 54 7B 81 3G 10G 55 6B 82 2G 9G 56 6A 83 1J 11F 57 5B 84 2J 11G 58 5A 85 3K 32 9F 59 4A 86 3J 33 10F 60 5C 87 2K 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D
CY7C1292DV18 CY7C1294DV18 Power Up Sequence in QDR II SRAM [16, 17] DLL Constraints QDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. ■ DLL uses K clock as its synchronizing input. The input should have low phase jitter, which is specified as tKC Var. ■ The DLL functions at frequencies down to 80 MHz. ■ If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior.
CY7C1292DV18 CY7C1294DV18 Maximum Ratings Neutron Soft Error Immunity Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V Supply Voltage on VDDQ Relative to GND.......–0.
CY7C1292DV18 CY7C1294DV18 AC Input Requirements Over the Operating Range Min Typ Max Unit VIH Parameter Input HIGH Voltage Description Test Conditions VREF + 0.2 – – V VIL Input LOW Voltage – – VREF - 0.2 V Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CO Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 1.8V VDDQ = 1.
CY7C1292DV18 CY7C1294DV18 Switching Characteristics Over the Operating Range[23, 24] Cypress Consortium Parameter Parameter Description 250 MHz Min. Max. 200 MHz Min. Max. 167 MHz Min. Max. Unit tPOWER tKHKH VDD(Typical) to the first Access[25] tCYC tKHKL K Clock and C Clock Cycle Time 4.0 6.3 5.0 7.9 6.0 7.9 ns tKH tKLKH Input Clock (K/K and C/C) HIGH 1.6 – 2.0 – 2.4 – ns tKL tKHKH 1.6 – 2.0 – 2.
CY7C1292DV18 CY7C1294DV18 Switching Waveforms Figure 5.
CY7C1292DV18 CY7C1294DV18 Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors.
CY7C1292DV18 CY7C1294DV18 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 TOP VIEW BOTTOM VIEW PIN 1 CORNER PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 Ø0.08 M C Ø0.25 M C A B A Ø0.50 B 11 10 9 8 7 6 5 4 -0.06 +0.14 3 (165X) 2 1 C A D B E C 1.00 F D 15.00±0.10 G E H F K L G 14.00 15.00±0.10 J H J M K N L 7.00 P M R N P A R A 1.00 5.00 B 13.00±0.10 1.40 MAX. SEATING PLANE C 0.15 C 0.53±0.05 0.36 0.25 C 10.00 B 13.00±0.10 0.
CY7C1292DV18 CY7C1294DV18 Document History Page Document Title: CY7C1292DV18/CY7C1294DV18 9-Mbit QDR® II SRAM 2-Word Burst Architecture Document Number: 001-00350 Rev. ECN No. Submission Date Orig. of Change ** 380737 See ECN SYT New data sheet *A 485631 See ECN NXR Converted from Preliminary to Final Removed 300MHz Speed Bin.
CY7C1292DV18 CY7C1294DV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive PSoC Solutions cypress.com/go/clocks psoc.cypress.com/solutions cypress.
Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Cypress Semiconductor: CY28517ZXCT CY7C1292DV18-167BZC CY7C1294DV18-167BZC
