Specifications

CY14B256K
Document Number: 001-06431 Rev. *G Page 8 of 24
Interrupts
The CY14B256K provides three potential interrupt sources.
They include the watchdog timer, the power monitor, and the
clock or calendar alarm. Each is individually enabled and
assigned to drive the INT pin. In addition, each has an associated
flag bit that the host processor uses to determine the cause of
the interrupt. Some of the sources have additional control bits
that determine functional behavior. In addition, the pin driver has
three bits that specify its behavior when an interrupt occurs.
Each of the three interrupts have a source and an enable. Both
the source and the enable are active (true high) to generate an
interrupt output. Only one source is necessary to drive the pin.
The user identifies the source by reading the Flags or Control
registers that contains the flags associated with each source. All
flags are cleared to ‘0’ when the register is read. The flags are
cleared only after a complete read cycle (WE high). The power
monitor has two programmable settings that is explained in the
“Power Monitor” on page 7.
When an interrupt source is active, the pin driver determines the
behavior of the output. It has two programmable settings as
shown in the following sections. Pin driver control bits are located
in the Interrupts register.
According to the programming selections, the pin is driven in the
backup mode for an alarm interrupt. In addition, the pin is an
active LOW (open drain) or an active HIGH (push pull) driver. If
programmed for operation during backup mode, it is only active
LOW. Lastly, the pin provides a one shot function so that the
active condition is a pulse or a level condition. In one shot mode,
the pulse width is internally fixed at approximately 200 ms. This
mode is intended to reset a host microcontroller. In Level mode,
the pin goes to its active polarity until the user reads the Flags or
Control registers. This mode is used as an interrupt to a host
microcontroller. The Interrupt register is initialized to 00h. The
control bits are summarized as follows:
Watchdog Interrupt Enable - WIE. When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog time out occurs. When WIE is set to ‘0’, the watchdog
timer affects only the internal flag.
Alarm Interrupt Enable - AIE. When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When set to ‘0’, the alarm
match only affects to internal flag.
Power Fail Interrupt Enable - PFE. When set to ‘1’, the power
fail monitor drives the pin and an internal flag. When set to ‘0’,
the power fail monitor affects only the internal flag.
High/Low - H/L
. When set to a ‘1’, the INT pin is active HIGH
and the driver mode is push pull. The INT pin drives high only
when V
CC
is greater than V
SWITCH
. When set to a ‘0’, the INT pin
is active LOW and the drive mode is open drain. Active LOW
(open drain) is operational even in battery backup mode.
Pulse/Level - P/L. When set to a ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to a
‘0’, the INT pin is driven high or low (determined by H/L) until the
Flags or Control register is read.
When an enabled interrupt source activates the INT pin, an
external host reads the Flags or Control registers to determine
the cause. Remember that all flags are cleared when the register
is read. If the INT pin is programmed for Level mode, then the
condition clears and the INT pin returns to its inactive state. If the
pin is programmed for Pulse mode, then reading the flag also
clears the flag and the pin. The pulse does not complete its
specified duration if the Flags or Control register is read. If the
INT pin is used as a host reset, then the Flags or Control register
is not read during a reset.
During a power on reset with no battery, the Interrupt register is
automatically loaded with the value 24h. This causes power fail
interrupt to be enabled with an active low pulse.
Flags Register - The Flags register has three flag bits: WDF, AF,
and PF. These flag bits are initialized to 00h. These flags are set
by the watchdog time out, alarm match, or power fail monitor
respectively. The processor either polls this register or enable to
inform the interrupts when a flag is set. The flags are automati-
cally reset when the register is read.
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