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Specifications

ManualsBrandsCypress Semiconductor ManualsComputer equipmentCY14B256K
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CY14B256K
Document Number: 001-06431 Rev. *G Page 7 of 24
To determine how to set the calibration, one may set the CAL bit
in the Flags register at 0x7FF0 to ‘1’ that causes the INT pin to
toggle at a nominal 512 Hz. Any deviation measured from the
512 Hz indicates the degree and direction of the required
correction. For example, a reading of 512.010124 Hz indicates
a +20 ppm error, requiring to load a –10 (001010) into the
Calibration register. Note that setting or changing the Calibration
register does not affect the frequency test output frequency.
Alarm
The alarm function compares user programmed values to the
corresponding time-of-day values. When a match occurs, the
alarm event occurs. The alarm drives an internal flag, AF, and
may drive the INT pin if desired.
There are four alarm match fields. They are date, hours, minutes,
and seconds. Each of these fields also has a Match bit that is
used to determine if the field is used in the alarm match logic.
Setting the Match bit to ‘0’ indicates that the corresponding field
is used in the match process.
Depending on the Match bits, the alarm occurs as specifically as
one particular second on one day of the month or as frequently
as once per second continuously. The MSb of each alarm
register is a Match bit. Selecting none of the Match bits (all 1s)
indicates that no match is required. The alarm occurs every
second. Setting the match select bit for seconds to ‘0’ causes the
logic to match the seconds alarm value to the current time of the
day. Since a match occurs for only one value per minute, the
alarm occurs once per minute. Likewise, setting the seconds and
minutes, Match bits cause an exact match of these values. Thus,
an alarm occurs once per hour. Setting seconds, minutes, and
hours causes a match once per day. Lastly, selecting all match
values causes an exact time and date match. Selecting other bit
combinations does not produce meaningful results. However,
the alarm circuit must follow the functions described.
There are two ways a user can detect an alarm event. They are
by reading the AF flag or monitoring the INT pin. The AF flag in
the Flags register at 0x7FF0 indicates that a date and time match
has occurred. The AF bit is set to ‘1’ when a match occurs.
Reading the Flags or Control register clears the Alarm flag bit
(and all others). A hardware interrupt pin is also used to detect
an alarm event.
Watchdog Timer
The Watchdog Timer is a free running down counter that uses
the 32 Hz clock (31.25 ms) derived from the crystal oscillator.
The oscillator is running for the watchdog to function. It begins
counting down from the value loaded in the Watchdog Timer
register.
The counter consists of a loadable register and a free running
counter. On power up, the watchdog time out value in register
0x7FF7 is loaded into the Counter Load register. Counting
begins on power up and restarts from the loadable value any time
the Watchdog Strobe (WDS) bit is set to ‘1’. The counter is
compared to the terminal value of ‘0’. If the counter reaches this
value, it causes an internal flag and an optional interrupt output.
You can prevent the time out interrupt by setting WDS bit to ‘1’
prior to the counter reaching ‘0’. This causes the counter to
reload with the watchdog time out value and to be restarted. As
long as the user sets the WDS bit prior to the counter reaching
the terminal value, the interrupt and flag never occur.
New time out values are written by setting the watchdog write bit
to ‘0’. When the WDW
is ‘0’ (from the previous operation), new
writes to the watchdog time out value bits D5-D0 enable to
modify the time out value. When WDW
is a ‘1’, writes to bits
D5-D0 are ignored. The WDW
function enables a user to set the
WDS bit without concern that the watchdog timer value is
modified. A logical diagram of the watchdog timer is shown in
Figure 3. Note that setting the watchdog time out value to ‘0’ is
otherwise meaningless and therefore disables the watchdog
function.
The output of the watchdog timer is the flag bit WDF that is set if
the watchdog is allowed to time out. The flag is set upon a
watchdog time out and cleared when the user reads the Flags or
Control registers. If the watchdog time out occurs, the user also
enables an optional interrupt source to drive the INT pin.
Power Monitor
The CY14B256K provides a power management scheme with
power fail interrupt capability. It also controls the internal switch
to backup power for the clock and protects the memory from low
V
CC
access. The power monitor is based on an internal band gap
reference circuit that compares the V
CC
voltage to various
thresholds.
As described in the “AutoStore Operation” on page 3, when
V
SWITCH
is reached as V
CC
decays from power loss, a data store
operation is initiated from SRAM to the nonvolatile elements,
securing the last SRAM data state. Power is also switched from
VCC to the backup supply (battery or capacitor) to operate the
RTC oscillator.
When operating from the backup source, no data is read or
written and the clock functions are not available to the user. The
clock continues to operate in the background. Updated clock
data is available to the user after VCC is restored to the device
and t
HRECALL
delay (see “AutoStore or Power Up RECALL” on
page 17).
Figure 3. Watchdog Timer Block Diagram
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