Specifications

CY14B256K
Document Number: 001-06431 Rev. *G Page 6 of 24
Clock Operations
The Clock registers maintain time up to 9,999 years in one
second increments. The user sets the time to any calendar time
and the clock automatically keeps track of days of the week,
month, leap years, and century transitions. There are eight
registers dedicated to the clock functions that are used to set
time with a write cycle and to read time during a read cycle.
These registers contain the time of day in BCD format. Bits
defined as ‘0’ are currently not used and are reserved for future
use by Cypress.
Reading the Clock
The double buffered RTC register structure reduces the chance
of reading incorrect data from the clock. But stop internal updates
to the CY14B256K Clock registers before reading clock data to
prevent the reading of data in transition. Stopping the internal
register updates does not affect clock accuracy. The update
process is stopped by writing a ‘1’ to the read bit R (in the Flags
register at 0x7FF0) and does not restart until a ‘0’ is written to the
read bit. The RTC registers is then read while the internal clock
continues to run. Within 20 ms after a ‘0’ is written to the read bit,
all CY14B256K registers are simultaneously updated.
Setting the Clock
Setting the write bit W (in the Flags register at 0x7FF0) to a ‘1’
stops updates to the CY14B256K registers. The correct day,
date, and time is then written into the registers in 24 hour BCD
format. The time written is referred to as the Base Time. This
value is stored in nonvolatile registers and used in calculation of
the current time. Resetting the write bit to ‘0’ transfers those
values to the actual clock counters after which the clock resumes
normal operation.
Backup Power
The RTC in the CY14B256K is used for permanently powered
operation. Either the V
RTCcap
or V
RTCbat
pin is connected
depending on whether a capacitor or battery is chosen for the
application. When primary power, V
CC
, fails and drops below
V
SWITCH
, the device switches to the backup power supply.
The clock oscillator uses very little current to maximize the
backup time available from the backup source. Regardless of
clock operation with the primary source removed, the data stored
in nvSRAM is secure, as it is stored in the nonvolatile elements
when power was lost.
During backup operation, the CY14B256K consumes a
maximum of 300 nA at 2V. Capacitor or battery values are
chosen according to the application. Backup time values, based
on maximum current specifications, are shown in Table 2 on
page 6. Nominal times are approximately three times longer.
Using a capacitor has the advantage of recharging the backup
source each time the system is powered up. If a battery is used,
use a 3V lithium and the CY14B256K only sources current from
the battery when the primary power is removed. The battery does
not, however, recharge at any time by the CY14B256K. The
battery capacity is chosen for total anticipated cumulative down
time required over the life of the system.
Stopping and Starting the Oscillator
The OSCEN bit in Calibration register at 0x7FF8 controls the
starting and stopping of the oscillator. This bit is nonvolatile and
shipped to customers in the enabled (set to ‘0’) state. To preserve
battery life while system is in storage, OSCEN
is set to a ‘1’. This
turns off the oscillator circuit, extending the battery life. If the
OSCEN bit goes from disabled to enabled, it takes approximately
five seconds (10 seconds max) for the oscillator to start.
The CY14B256K has the ability to detect oscillator failure. This
is recorded in the OSCF (Oscillator Failed bit) of the Flags
register at address 0x7FF0. When the device is powered on (V
CC
goes above V
SWITCH
), the OSCEN bit is checked for enabled
status. If the OSCEN
bit is enabled and the oscillator is not
active, the OSCF bit is set. The user must check for this condition
and then write a ‘0’ to clear the flag. In addition to setting the
OSCF flag bit, the Time registers are reset to the Base Time (for
more information, see “Setting the Clock” on page 6): the value
last written to the time keeping registers. The Control or
Calibration register and the OSCEN
bit are not affected by the
oscillator failed condition.
If the voltage on the backup supply (either V
RTCcap
or V
RTCbat
)
falls below its minimum level, the oscillator may fail, leading to
the oscillator failed condition that is detected when system power
is restored.
The value of OSCF is reset to ‘0’ when the time registers are
written for the first time. This initializes the state of this bit that is
set when the system is first powered on.
Calibrating the Clock
The RTC is driven by a quartz controlled oscillator with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal usually specified to 35 ppm limits at 25°C. This error
equates to +1.53 minutes per month. The CY14B256K employs
a calibration circuit that improves the accuracy to +1/–2 ppm at
25°C. The
calibration circuit adds or subtracts counts from the
oscillator divider circuit.
The number of pulses that are suppressed (subtracted, negative
calibration) or split (added, positive calibration) depends upon
the value loaded into the five calibration bits found in Calibration
register at 0x7FF8. Adding counts speeds the clock up and
subtracting counts slows the clock down. The calibration bits
occupy the five lower order bits in the Control register 8. These
bits are set to represent any value between ‘0’ and 31 in binary
form. Bit D5 is a sign bit, where a ‘1’ indicates positive calibration
and a ‘0’ indicates negative calibration. Calibration occurs within
a 64 minute cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by 128 or
lengthened by 256 oscillator cycles.
If a binary ‘1’ is loaded into the register, only the first two minutes
of the 64 minute cycle is modified. If a binary 6 is loaded, the first
12 are affected, and so on. Therefore, each calibration step has
the effect of adding 512 or subtracting 256 oscillator cycles for
every 125, 829,120 actual oscillator cycles, that is, 4.068 or
–2.034 ppm of adjustment per calibration step in the Calibration
register.
Table 2. RTC Backup Time
Capacitor Value Backup Time
0.1F 72 hours
0.47F 14 days
1.0F 30 days
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