Specifications

CY14B256K
Document Number: 001-06431 Rev. *G Page 5 of 24
Noise Considerations
The CY14B256K is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
CC
and V
SS
using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Low Average Active Power
CMOS technology provides CY14B256K which enables drawing
less current when it is cycled at times longer than 50 ns. Figure 2
shows the relationship between I
CC
and READ and/or WRITE
cycle time. Worst case current consumption is shown for
commercial temperature range, V
CC
= 3.6V, and chip enable at
maximum frequency. Only standby current is drawn when the
chip is disabled. The overall average current drawn by the
CY14B256K depends on the following items:
1. 1The duty cycle of chip enable
2. The overall cycle rate for accesses
3. The ratio of READs to WRITEs
4. The operating temperature
5. The V
CC
level
6. IO loading
.
Real Time Clock Operation
nvTIME Operation
The CY14B256K consists of internal registers that contain clock,
alarm, watchdog, interrupt, and control functions. Internal double
buffering of the clock and the clock/timer information registers
prevents accessing transitional internal clock data during a read
or write operation. Double buffering also circumvents disrupting
normal timing counts or clock accuracy of the internal clock while
accessing clock data. Clock and Alarm registers store data in
BCD format.
Table 1. Mode Selection
CE WE OE
A13–A0 Mode IO Power
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active I
CC2
[1, 2, 3]
L H L 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
[1, 2, 3]
Figure 2. Current versus Cycle Time
Notes
1. The six consecutive address locations are in the order listed.WE
is HIGH during all six cycles to enable a nonvolatile cycle.
2. While there are 15 address lines on the CY14B256K, only the lower 14 lines are used to control software modes.
3. IO state depends on the state of OE
. The IO table shown is based on OE Low.
[+] Feedback