Specifications

CY14B256K
Document Number: 001-06431 Rev. *G Page 16 of 24
AC Switching Characteristics
Parameter
Description
25 ns Part 35 ns Part 45 ns Part
Unit
Min Max Min Max Min Max
Cypress
Parameter
Alt.
Parameter
SRAM Read Cycle
t
ACE
t
ACS
Chip Enable Access Time 25 35 45 ns
t
RC
[11]
t
RC
Read Cycle Time 25 35 45 ns
t
AA
[12]
t
AA
Address Access Time 25 35 45 ns
t
DOE
t
OE
Output Enable to Data Valid 12 15 20 ns
t
OHA
[12]
t
OH
Output Hold After Address Change 3 3 3 ns
t
LZCE
[13]
t
LZ
Chip Enable to Output Active 3 3 3 ns
t
HZCE
[13]
t
HZ
Chip Disable to Output Inactive 10 13 15 ns
t
LZOE
[13]
t
OLZ
Output Enable to Output Active 0 0 0 ns
t
HZOE
[13]
t
OHZ
Output Disable to Output Inactive 10 13 15 ns
t
PU
[10]
t
PA
Chip Enable to Power Active 0 0 0 ns
t
PD
[10]
t
PS
Chip Disable to Power Standby 25 35 45 ns
SRAM Write Cycle
t
WC
t
WC
Write Cycle Time 25 35 45 ns
t
PWE
t
WP
Write Pulse Width 20 25 30 ns
t
SCE
t
CW
Chip Enable To End of Write 20 25 30 ns
t
SD
t
DW
Data Setup to End of Write 10 12 15 ns
t
HD
t
DH
Data Hold After End of Write 0 0 0 ns
t
AW
t
AW
Address Setup to End of Write 20 25 30 ns
t
SA
t
AS
Address Setup to Start of Write 0 0 0 ns
t
HA
t
WR
Address Hold After End of Write 0 0 0 ns
t
HZWE
[13, 14]
t
WZ
Write Enable to Output Disable 10 13 15 ns
t
LZWE
[13]
t
OW
Output Active After End of Write 3 3 3 ns
Notes
10. These parameters are guaranteed but not tested.
11. WE is HIGH during SRAM Read Cycles.
12. Device is continuously selected with CE and OE both Low.
13. Measured ±200 mV from steady state output voltage.
14. If WE is Low when CE goes Low, the outputs remain in the High Impedance State.
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