Specifications

CY14B256K

Document Number: 001-06431 Rev. *G Page 13 of 24

0x7FF0

Flags

D7 D6 D5 D4 D3 D2 D1 D0

WDFAF PFOSCF0CALW R

WDF Watchdog Timer Flag. This read only bit is set to ‘1’ when the watchdog timer is allowed to reach ‘0’ without being

reset by the user. It is cleared to ‘0’ when the Flags or Control register is read.

AF Alarm Flag. This read only bit is set to ‘1’ when the time and date match the values stored in the alarm registers with

the match bits = 0. It is cleared when the Flags or Control register is read.

PF Power Fail Flag. This read only bit is set to ‘1’ when power falls below the power fail threshold V

SWITCH

. It is cleared

to ‘0’ when the Flags or Control register is read.

OSCF Oscillator Fail Flag. Set to ‘1’ on power up only if the oscillator is not running in the first 5 ms of power on operation.

This indicates that time counts are no longer valid. The user must reset this bit to ‘0’ to clear this condition. The chip

does not clear this flag. This bit survives power cycles.

CAL Calibration Mode. When set to ‘1’, a 512 Hz square wave is output on the INT pin. When set to ‘0’, the INT pin

resumes normal operation. This bit defaults to ‘0’ (disabled) on power up.

W Write Time. Setting the W bit to ‘1’ freezes updates of the time keeping registers. The user then writes them with

updated values. Setting the W bit to ‘0’ transfers the contents of the time registers to the time keeping counters. The

W bit enables writes to RTC, Alarm, Calibration, Interrupt, and Flag registers.

[ 5]

R Read Time. Setting the R bit to ‘1’ copies a static image of the time keeping registers and places them in a holding

from ‘0’ to ‘1’ causes the time keeping capture, so the bit is returned to ‘0’ prior to reading again.

Table 4. Register Map Detail (continued)

Note

5. W bit is set to write to any of the RTC registers except the Flag register (0X1FFF1 to 0X1FFFF).

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