Specifications

CY14B256K
Document Number: 001-06431 Rev. *G Page 11 of 24
0x7FFB
Time Keeping - Hours
D7 D6 D5 D4 D3 D2 D1 D0
12/24 0 10s Hours Hours
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and operates from 0 to 9;
upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0–23.
0x7FFA
Time Keeping - Minutes
D7 D6 D5 D4 D3 D2 D1 D0
0 10s Minutes Minutes
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble
contains the upper minutes digit and operates from 0 to 5. The range for the register is 0–59.
0x7FF9
Time Keeping - Seconds
D7 D6 D5 D4 D3 D2 D1 D0
0 10s Seconds Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble
contains the upper digit and operates from 0 to 5. The range for the register is 0–59.
0X7FF8
Calibration/Control
D7 D6 D5 D4 D3 D2 D1 D0
OSCEN
0 Calibration
Sign
Calibration
OSCEN Oscillator Enable. When set to ‘1’, the oscillator is halted. When set to ‘0’, the oscillator runs. Disabling the oscillator
saves battery or capacitor power during storage. On a no battery power up, this bit is set to ‘0’.
Calibration
Sign
Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time base.
Calibration These five bits control the calibration of the clock.
0x7FF7
WatchDog Timer
D7 D6 D5 D4 D3 D2 D1 D0
WDS WDW WDT
WDS Watchdog Strobe. Setting this bit to ‘1’ reloads and restarts the watchdog timer. Setting the bit to ‘0’ has no affect.
The bit is cleared automatically when the watchdog timer is reset. The WDS bit is write only. Reading it always returns
a ‘0’.
WDW
Watchdog Write Enable. Setting this bit to ‘1’ masks the watchdog time out value (WDT5–WDT0) so it cannot be
written. This enables the user to strobe the watchdog without disturbing the time out value. Setting this bit to ‘0’
allows bits 5–0 to be written on the next write to the Watchdog register. The new value is loaded on the next internal
watchdog clock after the write cycle is complete. This function is explained in detail in the “Watchdog Timer” on
page 7.
WDT Watchdog Time Out Selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents
a multiplier of the 32 Hz count (31.25 ms). The minimum range or time out value is 31.25 ms (a setting of ‘1’) and
the maximum time out is two seconds (setting of 3 Fh). Setting the Watchdog Timer register to ‘0’ disables the timer.
These bits are written only if the WDW bit is cleared to ‘0’ on a previous cycle.
Table 4. Register Map Detail (continued)
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