User guide

30 CY3687 MoBL-USB FX2LP18 Development Kit User Guide, Doc. # 001-68582 Rev. *B

Development Kit Contents

4.6 Hardware

The directory contains MoBL-USB hardware schematic, PCB, Layout, gerber and PCB BOM files.

Following are the files in this directory.

4.7 SuiteUSB

This folder contains SuiteUSB 3.4.7 installer package and a sample Cypress Software License

agreement document. The software is installed as part ofCY3687 MoBL-USB FX2LP18 Kit installer

and the contents are by default located at C:\Cypress\Cypress SuiteUSB 3.4.7.The package con-

tains C++ and C# .NET application tools to communicate with MoBL-USB FX2LP18 device. Also it

contains Cypress generic USB drivers (3.4.7). The package contains unsigned drivers. The signed

driver packages supplied in the /Driver directory should be used to try the code examples explained

in MoBL-USB Development Kit Firmware Examples chapter on page 59.

Table 4-4. List of Hardware Files in MoBL-USB FX2LP18 Development Kits

S.No: Files Description

CY3687_MoBL-

USB_FX2LP18_DVK_schematic.pdf/

CY3687_MoBL-

USB_FX2LP18_DVK_Schematic.DSN

This file is Non-editable (pdf) and editable (.DSN) version

of the schematic source file. The .DSN file can be viewed

using Orcad software.

CY3687_MoBL-

USB_FX2LP18_DVK_Gerber.zip

This .zip files contains PCB images of different layers of

the MoBL-USB FX2LP18 development board PCB.

CY3687_MoBL-

USB_FX2LP18_DVK_BOM.pdf/

CY3687_MoBL-

USB_FX2LP18_DVK_BOM.xls

This file contains components like resistors, capacitors,

jumpers, etc., used in designing MoBL-USB FX2LP18

development board

CY3687_MoBL-

USB_FX2LP18_DVK_Board_Layout.brd

/CY3687_MoBL-

USB_FX2LP18_DVK_Board_Layout.pdf

These files contain the PCB layout of MoBL-USB

FX2LP18 development board.The editable layout file

(.brd) can be viewed using Allegro software tools.

PDC-9022-A-Dimension.PDF,

PDC-9022-REVA.pdf, CY3681-

2_ASSEMBLY.pdf, and PDC-9022-A.zip

These files are part of PROTO board daughter card

designed to provide a sample prototype area for validat-

ing communication between GPIF/Slave FIFO interface

and External device.