Data Sheet
Table Of Contents
- CYBT-343052-02, EZ-BT WICED Module
- General Description
- Benefits
- More Information
- Contents
- Overview
- Pad Connection Interface
- Recommended Host PCB Layout
- Module Connections
- Connections and Optional External Components
- Functional Description
- Integrated Radio Transceiver
- Peripheral and Communication Interfaces
- Keyboard Scanner
- Clock Frequencies
- GPIO Port
- PWM
- Power Management Unit
- Electrical Characteristics
- Chipset RF Specifications
- Timing and AC Characteristics
- Environmental Specifications
- Regulatory Information
- Packaging
- Ordering Information
- Acronyms
- Document Conventions
- Document History Page
- Sales, Solutions, and Legal Information
Document Number: 002-28053 Rev. ** Page 31 of 47
CYBT-343052-02
SPI Timing
The SPI interface supports clock speeds up to 12 MHz
Table 19 and Figure 14 show the timing requirements when operating in SPI Mode 0 and 2, and SPI Mode 1 and 3, respectively.
Figure 14. SPI Timing – Mode 0 and 2
Table 19. SPI Mode 0 and 2
Reference Characteristics Min Max Unit
1
Time from slave assert SPI_INT to master assert SPI_CSN
(DirectRead)
0
ns
2
Time from master assert SPI_CSN to slave assert SPI_INT
(DirectWrite)
0
3 Time from master assert SPI_CSN to first clock edge 20
4 Setup time for MOSI data lines 8 ½ SCK
5 Hold time for MOSI data lines 8 ½ SCK
6 Time from last sample on MOSI/MISO to slave deassert SPI_INT 0 100
7 Time from slave deassert SPI_INT to master deassert SPI_CSN 0
8 Idle time between subsequent SPI transactions 1 SCK
2
SPI_CSN
SPI_INT
(DirectWrite)
SPI_CLK
(Mode 0)
SPI_MOSI
First Bit
SPI_MISO
Not Driven
First Bit
Second Bit
Second Bit
Last bit
Last bit
1
3
4
5
SPI_CLK
(Mode 2)
SPI_INT
(DirectRead)
Not Driven