Data Sheet

Document Number: 002-28053 Rev. ** Page 20 of 47
CYBT-343052-02
Peripheral and Communication Interfaces
I
2
C Communication Interface
The CYBT-343052-02 provides a 2-pin master I
2
C interface, which can be used to retrieve configuration information from an external
EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse
devices. This interface is compatible with I
2
C slave devices. I
2
C does not support multimaster capability or flexible wait-state insertion
by either master or slave devices.
The following transfer clock rates are supported by the I
2
C:
■ 100 kHz
■ 400 kHz
■ 800 kHz (not a standard I
2
C-compatible speed.)
■ 1 MHz (Compatibility with high-speed I
2
C-compatible devices is not guaranteed.)
The following transfer types are supported by the I
2
C:
■ Read (Up to 8 bytes can be read)
■ Write (Up to 8 bytes can be written)
■ Read-then-Write (Up to 8 bytes can be read and up to 8 bytes can be written)
■ Write-then-Read (Up to 8 bytes can be written and up to 8 bytes can be read)
Hardware controls the transfers, requiring minimal firmware setup and supervision.
The clock pad (I2C_SCL) and data pad 2 (I2C_SDA) are both open-drain I/O pins. Pull-up resistors, external to the CYBT-343052-02,
are required on both the SCL and SDA pad for proper operation.
HCI UART Interface
The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 57600 bps to
6 Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via a vendor-specific UART
HCI command. The CYBT-343052-02 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates.
The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.
The UART clock default setting is 24 MHz, and can be configured to run as high as 48 MHz to support up to 6 Mbps. The baud rate
of the CYBT-343052-02UART is controlled by two values. The first is a UART clock divisor (set in the DLBR register) that divides the
UART clock by an integer multiple of 16. The second is a baud rate adjustment (set in the DHBR register) that is used to specify a
number of UART clock cycles to stuff in the first or second half of each bit time. Up to eight UART cycles can be inserted into the first
half of each bit time, and up to eight UART clock cycles can be inserted into the end of each bit time.
Table 9 contains example values to generate common baud rates with a 24 MHz UART clock.
Table 9. Common Baud Rate Examples, 24 MHz Clock
Baud Rate (bps)
Baud Rate Adjustment
Mode Error (%)
High Nibble Low Nibble
3M 0xFF 0xF8 High rate 0.00
2M 0XFF 0XF4 High rate 0.00
1M 0X44 0XFF Normal 0.00
921600 0x05 0x05 Normal 0.16
460800 0x02 0x02 Normal 0.16
230400 0x04 0x04 Normal 0.16
115200 0x00 0x00 Normal 0.16
57600 0x00 0x00 Normal 0.16
38400 0x01 0x00 Normal 0.00