Data Sheet
Table Of Contents
- CYBT-343052-02, EZ-BT WICED Module
- General Description
- Benefits
- More Information
- Contents
- Overview
- Pad Connection Interface
- Recommended Host PCB Layout
- Module Connections
- Connections and Optional External Components
- Functional Description
- Integrated Radio Transceiver
- Peripheral and Communication Interfaces
- Keyboard Scanner
- Clock Frequencies
- GPIO Port
- PWM
- Power Management Unit
- Electrical Characteristics
- Chipset RF Specifications
- Timing and AC Characteristics
- Environmental Specifications
- Regulatory Information
- Packaging
- Ordering Information
- Acronyms
- Document Conventions
- Document History Page
- Sales, Solutions, and Legal Information
Document Number: 002-28053 Rev. ** Page 17 of 47
CYBT-343052-02
Test Mode Support
The CYBT-343052-02 fully supports the Bluetooth Test mode as described in
Part I:1 of the Specification of the Bluetooth System
Version 3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.
In addition to the standard Bluetooth Test Mode, the CYBT-343052-02 also supports enhanced testing features to simplify RF
debugging and qualification and type-approval testing. These features include:
■ Fixed frequency carrier wave (unmodulated) transmission
❐ Simplifies some type-approval measurements (Japan)
❐ Aids in transmitter performance analysis
■ Fixed frequency constant receiver mode
❐ Receiver output directed to I/O pin
❐ Allows for direct BER measurements using standard RF test equipment
❐ Facilitates spurious emissions testing for receive mode
■ Fixed frequency constant transmission
❐ 8-bit fixed pattern or PRBS-9
❐ Enables modulated signal measurements with standard RF test equipment.
Frequency Hopping Generator
The frequency hopping sequence generator selects the correct hopping channel number based on the link controller state, Bluetooth
clock, and device address.
Microcontroller Unit
The CYW20735B1 microprocessor unit runs software from the link control (LC) layer up to the host controller interface (HCI). The
microprocessor is a Cortex-M4 32-bit RISC processor with embedded ICE-RT debug and serial wire debug (SWD) interface units.
The microprocessor also includes 2 MB of ROM memory for program storage and 384 KB of RAM for data scratch-pad. The internal
ROM provides flexibility during power-on reset to enable the same device to be used in various configurations. At powerup, the
lower-layer protocol stack is executed from internal ROM.
External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions. The device also
supports the integration of user applications and profiles.
Floating Point Unit
CYW20735B1 includes the CM4 single precision IEEE-754 compliant floating point unit. For details, see the Cortex-M4 manual.
OTP Memory
The CYW20735B1 includes 2 KB of one-time programmable memory that can be used by the factory to store product-specific
information.
Note Use of OTP requires that a 3V supply be present at all times.
NVRAM Configuration Data and Storage
NVRAM contains configuration information about the customer application, including the following:
■ Fractional-N information
■ BD_ADDR
■ UART baud rate
■ SDP service record
■ File system information used for code, code patches, or data. The CYW20735B1 uses SPI Serial Flash for NVRAM storage.
Power-On Reset (POR)
The CYW20735B1 includes POR logic to allow the part to initialize correctly when power is applied. Figure 10 shows the sequence
used by the CYW20735B1 during initialization. An small external cap may be used on RESET_N to add delay as VDDIO ramps up.