User`s manual

CyberResearch
®
Motherboards MXGD Series
CyberResearch, Inc. 19
25 Business Park Drive P: [phone]; F: [phone]
Branford, CT USA www.cyberresearch.com
direction simultaneously, for an aggregate of 8 GB/s when x16.
 PCI Express* Graphics Extended Configuration Space. The first 256 bytes of
configuration space alias directly to the PCI Compatibility configuration space.
The remaining portion of the fixed 4-KB block of memory-mapped space
above that (starting at 100h) is known as extended configuration space.
 PCI Express Enhanced Addressing Mechanism. Accessing the device
configuration pace in a flat memory mapped fashion.
 Automatic discovery, negotiation, and training of link out of reset
 Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
 Supports traditional AGP style traffic (asynchronous non-snooped, PCI
Express relaxed ordering)
 Hierarchical PCI-compliant configuration mechanism for downstream devices
(i.e., normal PCI 2.3 Configuration space as a PCI-to-PCI bridge)
 Supports “static” lane numbering reversal. This method of lane reversal is
controlled by a Hardware Reset strap, and reverses both the receivers and
transmitters for all lanes (e.g., TX[15]->TX[0], RX[15]->RX[0]). This method is
transparent to all external devices and is different than lane reversal as
defined in the PCI Express Specification. In particular, link initialization is not
affected by static lane reversal.
2.4.4 Intel
®
Q965 Direct Media Interface (DMI)
Intel
®
Q965 northbridge GMCH is connected to the Intel
®
ICH8DO Southbridge Chipset
through the chip-to-chip Direct Media Interface (DMI). Features of the Intel
®
Q965 DMI are
listed below:
 chip-to-chip connection interface to Intel ICH8
 2GB/s (1GB/s in each direction) bus speed
 32-bit downstream address
 100 MHz reference clock (shared with PCI Express Graphics Attach)
 APIC and MSI interrupt messaging support
 Message Signaled Interrupt (MSI) messages
 SMI, SCI and SERR error indication
 DMA, floppy drive, and LPC bus master