User`s manual

MMGA Series CyberResearch
®
Motherboards
22 ©Copyright 2009 CyberResearch, Inc.

Trusted Platform Module (TPM) connector
2.5.6 Intel
®
ICH9DO PCI Interface
The PCI interface on the ICH9DO is compliant with the PCI Revision 2.3 implementation.
Some of the features of the PCI interface are listed below.
 PCI Revision 2.3 compliant
 33MHz
 5V tolerant PCI signals (except PME#)
 Integrated PCI arbiter supports up to four PCI bus masters
The PCI bus masters are interfaced to the following onboard components:
 Two PCI sockets
2.5.7 Intel
®
ICH9DO PCIe x4 Bus
The Intel® ICH9DO Southbridge chipset has six PCIe x1 lanes. The four PCIe lanes are
interfaced to one PCIe x4 slot on the MMGA motherboard.
One of the remaining PCIe x1 lanes is connected to an Intel® 82566DM GbE controller
and the other PCIe x1 lane is connected to an Intel® 82573L GbE controller.
For more detailed information, please refer to Section 2.6.3.
2.5.8 Intel
®
ICH9DO Real Time Clock
256 bytes of battery backed RAM is provided by the Motorola MC146818B real time clock
(RTC) integrated into the ICH9DO. The RTC operates on a 3V battery and 32.768KHz
crystal. The RTC keeps track of the time and stores system data even when the system is
turned off.