Specifications

Application Information (Continued)
CAPACITOR SELECTION
Use a 4.7µF or 10µF ceramic input capacitor. A 10µF ce-
ramic input capacitor is recommended if the PA represents a
load
<
14Ω. Use a 4.7µF ceramic output capacitor for getting
faster slew rates for output voltages from V
OUT
(min) to V
OUT
(max). Use X7R or X5R types, do not use Y5V. The rise
time for the voltage from V
OUT
(min) to V
OUT
(max) depends
on the slew rate of the error amp, switch peak current limit
and the value of the output capacitor. The time for the output
to change from V
OUT
(max) to V
OUT
(min) depends on R
LOAD
and C
OUT
. Use of tantalum capacitors is not recommended.
Ceramic capacitors provide an optimal balance between
small size, cost, reliability and performance for cell phones
and similar applications. A 22µF ceramic output capacitor
can be used in applications requiring fixed output voltages
and/or increased tolerance to heavy load transients. A 10µF
ceramic output capacitor can be used in applications where
the worst case load transient step is less than 200mA. Table
3 lists suggested capacitors and suppliers.
The input filter capacitor supplies current to the PFET switch
of the LM2614 in the first part of each cycle and reduces
voltage ripple imposed on the input power source. The out-
put filter capacitor smoothes out current flow from the induc-
tor to the load, helps maintain a steady output voltage during
transient load changes and reduces output voltage ripple.
These capacitors must be selected with sufficient capaci-
tance and sufficiently low ESR to perform these functions.
Parallel combinations of smaller value ceramic capacitors
can also be used on the output as long as the combined
value is at least 4.7µF for the application circuit in Figure 1.
The ESR, or equivalent series resistance, of the filter capaci-
tors is a major factor in voltage ripple.
TABLE 3. Suggested Capacitors and Their Suppliers
Model Type Vendor Phone FAX
C1, C2 (Input or Output Filter Capacitor)
JMK212BJ475MG Ceramic Taiyo-Yuden 847-925-0888 847-925-0899
LMK316BJ475ML Ceramic Taiyo-Yuden 847-925-0888 847-925-0899
C2012X5R0J475K Ceramic TDK 847-803-6100 847-803-6296
JMK325BJ226MM Ceramic Taiyo-Yuden 847-925-0888 847-925-0899
JMK212BJ106MG Ceramic Taiyo-Yuden 847-925-0888 847-925-0899
micro SMD PACKAGE ASSEMBLY AND USE
Use of the micro SMD package requires specialized board
layout, precision mounting and careful reflow techniques, as
detailed in National Semiconductor Application Note
AN-1112. Refer to the section Surface Mount Technology
(SMT) Assembly Considerations. For best results in assem-
bly, alignment ordinals on the PC board should be used to
facilitate placement of the device.
The pad style used with micro SMD package must be the
NSMD (non-solder mask defined) type. This means that the
solder-mask opening is larger than the pad size. This pre-
vents a lip that otherwise forms if the solder-mask and pad
overlap, from holding the device off the surface of the board
and interfering with mounting. See Application Note AN-1112
for specific instructions how to do this.
The 10-Bump package used for the LM2614 has 300 micron
solder balls and requires 10.82mil pads for mounting on the
circuit board. The trace to each pad should enter the pad
with a 90˚ entry angle to prevent debris from being caught in
deep corners. Initially, the trace to each pad should be
6–7mil wide, for a section approximately 6mil long, as a
thermal relief. Then each trace should neck up or down to its
optimal width. The important criterion is symmetry. This en-
sures the solder bumps on the LM2614 reflow evenly and
that the device solders level to the board. In particular,
special attention must be paid to the pads for bumps D3–B3.
Because PGND and PVIN are typically connected to large
copper planes, inadequate thermal reliefs can result in late
or inadequate reflow of these bumps.
The micro SMD package is optimized for the smallest pos-
sible size in applications with red or infrared opaque cases.
Because the micro SMD package lacks the plastic encapsu-
lation characteristic of larger devices, it is vulnerable to light.
Backside metalization and/or epoxy coating, along with
front-side shading by the printed circuit board, reduce this
sensitivity.
BOARD LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter
design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing to
EMI, ground bounce, and resistive voltage loss in the traces.
These can send erroneous signals to the DC-DC converter
IC, resulting in poor regulation or instability. Poor layout can
also result in reflow problems leading to poor solder joints
between the micro SMD package and board pads. Poor
solder joints can result in erratic or degraded performance.
Good layout for the LM2614 can be implemented by follow-
ing a few simple design rules.
1. Place the LM2614 on 10.82 mil (10.82/1000 in.) pads.
As a thermal relief, connect to each pad witha7mil
wide, approximately 7 mil long traces, and then incre-
mentally increase each trace to its optimal width. The
important criterion is symmetry to ensure the solder
bumps on the LM2614 reflow evenly (see micro SMD
Package Assembly and Use).
2. Place the LM2614, inductor and filter capacitors close
together and make the traces short. The traces between
these components carry relatively high switching cur-
rents and act as antennas. Following this rule reduces
radiated noise. Place the capacitors and inductor within
0.2 in. (5 mm) of the LM2614.
LM2614
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