Datasheet
20050 SW 112
th
Ave. Tualatin, Oregon 97062 phone 503.612.2300 fax 503.612.2382
rev.
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rev.
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DESCRIPTION: point of load converter
10 of 12
08/2007
PART NUMBER: VPOL5A-12-SIP
7.6 Input Capacitance at the Power Module
The VPOL5A-12-SIP converters must be connected to a low AC
source impedance. To avoid problems with loop stability source
inductance should be low. Also, the input capacitors should be placed
close to the converter input pins to de-couple distribution inductance.
However, the external input capacitors are chosen for suitable ripple
handling capability. Low ESR polymers are a good choice. They have
high capacitance, high ripple rating and low ESR (typical <100mohm).
Electrolytic capacitors should be avoided. Circuit as shown in Figure 10
represents typical measurement methods for ripple current. Input
reflected-ripple current is measured with a simulated source Inductance
of 1uH. Current is measured at the input of the module.
+Vin
Common
VPOL5A-12-SIP
220uF
ESR<0.1ohm
2*100uF
Tantalum
L1
1uH
+Power
Supply
To Oscilloscope
Figure 10. Input Reflected-Ripple Test Setup
7.7 Test Set-Up
The basic test set-up to measure parameters such as efficiency and
load regulation is shown in Figure 11. Things to note are that this
converter is non-isolated, as such the input and output share a common
ground. These grounds should be connected together via low
impedance ground plane in the application circuit. When testing a
converter on a bench set-up, ensure that -V
in and -Vo are connected
together via a low impedance short to ensure proper efficiency and load
regulation measurements are being made. When testing the CUI INC’s
VPOL5A-12-SIP under any transient conditions please ensure that the
transient response of the source is sufficient to power the equipment
under test. We can calculate the
Efficiency
Load regulation and line regulation.
The value of efficiency is defined as:
%100
IinVin
IoVo
Where: Vo is output voltage,
Io is output current,
Vin is input voltage,
Iin is input current.
The value of load regulation is defined as:
%100.
NL
NLFL
V
VV
reg =
Load
Where: V
FL
is the output voltage at full load
V
NL
is the output voltage at no load
The value of line regulation is defined as:
%100.
LL
LLHL
V
VV
reg =Line
Where: V
HL
is the output voltage of maximum input voltage at full load.
V
LL
is the output voltage of minimum input voltage at full load.
+Vin
Common
VPOL5A-12-SIP
47uF
+
Power
Supply
A
V
Current Meter
Voltage Meter
+Vo
Common
+Sense
Load
V
A
10UF
CERAMIC
Figure 11. VPOL5A-12-SIP Test Setup
_
x
_
x
x
x
x
ç =
For more information, please visit the product page.