Specifications

Legacy BIOS References
171
instruction. The saving of the context is necessary as IVE microcode uses all the
Itanium architecture registers.
When the IA-32 handler does an Iret instruction, this instruction is trapped by Itanium
architecture and the Itanium architecture trap handler restores the caller context and
returns through an RFI.
It is possible that IA-32 code may not do an Iret but does “ret 2.” There are several
ways to handle this situation. One way is to let the Itanium architecture handler point
the IA-32 stack to a deliberately and intentionally faulting instruction such as rep:HLT
(IA-32 opcode 0xf, 0xf4) and then take control in the Itanium architecture fault handler
to restore the context.
5.6.3.3 Assumptions
The previous topics in this section assumed that the platform has an 8259 PIC and an
IVE (Intel
®
value-added engine core that executes most of the IA-32 instructions). But
future processors may not have those elements. In that case, traditional mode can be
handled only by an IA-32 instruction emulator. One way of doing this handling is to set
the psr (processor status register) in such a way that execution of all IA-32 instructions
fault into native code and hence get emulated.
IVA-based interrupts include external interrupts, NMI, faults and traps. A unique vector
number 0,2,0x10 through 0xFF defines external interrupts. The list below in the
Description field is a list of IVA-based interrupts that may be used by the Framework.
Table 21 IVA-Based Interrupts Useable in the Framework
Type Name Description
External Interrupts INT 0 Unused
External Interrupt INT 2 Unused
External Interrupt INT 0x10- 0xFF Unused
Alternate Data TLB
Alternate Instruction TLB
Break Instruction Used
Data Access Rights
Data Access-Bit
Data Key Miss
Data Nested TLB
Data TLB
Debug Used
Dirty-Bit
Disable FP-Register
Floating-point Fault
Floating-point trap
General Exception Used
IA-32 Exception General IA-32 fault
IA-32 Interrupt IA-32 invalid opcode
IA-32 Interrupt IA-32 software interrupt