Specifications

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5.6.3.1 PAL-Based Interrupts
The table below lists the PAL-based interrupts for the Itanium® processor family.
Table 20 PAL-Based Interrupts
Type Name PALE Entry Description
Abort Machine Checks (MCA) PALE_CHECK An immediate action hardware error has
occurred.
Abort Processor Reset PALE_RESET A processor has been powered on or a reset
request sent to it.
Initialization
interrupts
INIT PALE_INIT A processor has received an initialization
interrupt.
Platform
Management
interrupts
PMI PALE_PMI A platform management request has been
received..
5.6.3.2 IVA-Based Interrupts
Itanium processors support a SAPIC component and an internal ITC (Interval Timer
Counter – AR44), which counts up at a fixed relationship to the processor clock
frequency. The controlling parameter for this internally delivered interrupt can be
programmed into ITV (CR72). When the ITC count reaches the value programmed into
the Interval Timer Match Register (ITM-CR1), the interval timer interrupt is raised. In
the SAPIC mode, they are directly delivered internally to the processor. This mechanism
is used to get the timer tick interrupt that is needed for EFI core operation.
Interruption Vector Table (IVA)–based interrupts function very differently in the Itanium
processor family but allow the management of traditional 8259-based interrupts. When
a hardware interrupt occurs, the processor switches to an alternate bank of registers,
loads the preinterrupt context to several control registers (such as ipsr, iip, and so on),
and then branches to a location pointed by cr.IVA + 0x3000. At this location, the
hardware interrupt management code starts executing. This code will read cr.ivr and if
the vector is 00, then it is a traditional 8259-generated interrupt. If it is nonzero, then it
is a SAPIC-programmed interrupt. The ITC interrupt mentioned earlier is one such thing
with a distinct SAPIC-supplied nonzero vector.
If it is a traditional interrupt, then the Itanium® architecture interrupt handler code will
do a non-cached one-byte load from a special cycle location at offset 0x1e00 from the
base of processor interrupt block region, which has been programmed into the processor
through a PAL call. Either the internal bus unit or the chipset would then recognize the
special cycle (for the Itanium processor family, the logic is in the processor) and will
produce two INTA bus cycles to 8259. The first cycle is ignored by 8259 as it is
programmed to 8086 mode by the CSM code/8259 INIT code (the first cycle will produce
a call 8085 opcode if 8259 is programmed into 8085 mode, which is not the case). The
8259 will respond to the second INTA cycle and will send the vector up the bus, and the
Itanium architecture code will read it by its special cycle one-byte load.
This Itanium architecture code has an option of processing this vector. The CSM design
must be such that the code reflects this option to 16-bit IA-32 code. This vector number
will be multiplied by 4 and code segment and offset shall be read. Itanium architecture
will save the machine context, including floating point registers, and then loads the CS
and IP value to the appropriate Itanium processor family registers and prepares the 16-
bit IA-32 code environment. The new stack and then the Itanium architecture code is
provided. Then it will branch to the Itanium architecture code with a special br.ia