Parts List/Tune Up Info

49
CC2642R
www.ti.com SWRS194G –JANUARY 2018 – REVISED APRIL 2020
Submit Documentation Feedback
Product Folder Links: CC2642R
Detailed Description
Copyright © 2018–2020, Texas Instruments Incorporated
6.8 Serial Peripherals and I/O
The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and TI's
synchronous serial interfaces. The SSIs support both SPI master and slave up to 4 MHz. The SSI
modules support configurable phase and polarity.
The UARTs implement universal asynchronous receiver and transmitter functions. They support flexible
baud-rate generation up to a maximum of 3 Mbps.
The I
2
S interface is used to handle digital audio and can also be used to interface pulse-density
modulation microphones (PDM).
The I
2
C interface is also used to communicate with devices compatible with the I
2
C standard. The I
2
C
interface can handle 100 kHz and 400 kHz operation, and can serve as both master and slave.
The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of
peripherals to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up
capable, have a programmable pullup and pulldown function, and can generate an interrupt on a negative
or positive edge (configurable). When configured as an output, pins can function as either push-pull or
open-drain. Five GPIOs have high-drive capabilities, which are marked in bold in Section 4. All digital
peripherals can be connected to any digital pin on the device.
For more information, see the CC13x2, CC26x2 SimpleLink™ Wireless MCU Technical Reference
Manual.
6.9 Battery and Temperature Monitor
A combined temperature and battery voltage monitor is available in the CC2642R device. The battery and
temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage
and respond to changes in environmental conditions as needed. The module contains window
comparators to interrupt the system CPU when temperature or supply voltage go outside defined
windows. These events can also be used to wake up the device from Standby mode through the Always-
On (AON) event fabric.
6.10 μDMA
The device includes a direct memory access (μDMA) controller. The μDMA controller provides a way to
offload data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and
the available bus bandwidth. The μDMA controller can perform a transfer between memory and
peripherals. The μDMA controller has dedicated channels for each supported on-chip module and can be
programmed to automatically perform transfers between peripherals and memory when the peripheral is
ready to transfer more data.
Some features of the μDMA controller include the following (this is not an exhaustive list):
• Highly flexible and configurable channel operation of up to 32 channels
• Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral
• Data sizes of 8, 16, and 32 bits
• Ping-pong mode for continuous streaming of data
6.11 Debug
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1)
interface. The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG.