Specifications
Table Of Contents
- ARM Debugger
- Brief Overview of Documents for New Users
- Warning
- Quick Start of the JTAG Debugger
- Troubleshooting
- FAQ
- Trace Extensions
- Symmetric Multiprocessing
- ARM Specific Implementations
- ARM specific SYStem Commands
- SYStem.BdmClock Define JTAG frequency
- SYStem.CLOCK Inform debugger about core clock
- SYStem.CONFIG Configure debugger according to target topology
- SYStem.CPU Select the used CPU
- SYStem.CpuAccess Run-time memory access (intrusive)
- SYStem.JtagClock Define JTAG frequency
- SYStem.LOCK Tristate the JTAG port
- SYStem.MemAccess Run-time memory access
- SYStem.Mode Establish the communication with the target
- SYStem.Option ABORTFIX Do not access 0x0-0x1f
- SYStem.Option AHBHPROT Select AHB-AP HPROT bits
- SYStem.Option AMBA Select AMBA bus mode
- SYStem.Option ASYNCBREAKFIX Asynchronous break bugfix
- SYStem.Option AXIACEEnable ACE enable flag of the AXI-AP
- SYStem.Option AXICACHEFLAGS Select AXI-AP CACHE bits
- SYStem.Option AXIHPROT Select AXI-AP HPROT bits
- SYStem.Option BUGFIX Breakpoint bug fix
- SYStem.Option BUGFIXV4 Asynch. break bug fix for ARM7TDMI-S REV4
- SYStem.Option BigEndian Define byte order (endianess)
- SYStem.Option BOOTMODE Define boot mode
- SYStem.Option CINV Invalidate the cache after memory modification
- SYStem.Option CFLUSH FLUSH the cache before step/go
- SYStem.Option CacheParam Define external cache
- SYStem.Option DACR Debugger ignores DACR access permission settings
- SYStem.Option DAPNOIRCHECK No DAP instruction register check
- SYStem.Option DAPREMAP Rearrange DAP memory map
- SYStem.Option DBGACK DBGACK active on debugger memory accesses
- SYStem.Option DBGNOPWRDWN DSCR bit 9 will be set when in debug mode
- SYStem.Option DBGUNLOCK Unlock debug register via OSLAR
- SYStem.Option DCDIRTY Bugfix for erroneously cleared dirty bits
- SYStem.Option DCFREEZE Disable data cache linefill in debug mode
- SYStem.Option DIAG Activate more data.log messages
- SYStem.Option DisMode Define disassembler mode
- SYStem.Option DynVector Dynamic trap vector interpretation
- SYStem.Option EnReset Allow the debugger to drive nRESET/nSRST
- SYStem.Option ETBFIXMarvell Read out on-chip trace data
- SYStem.Option ETMFIX Shift data of ETM scan chain by one
- SYStem.Option ETMFIXWO Bugfix for write-only ETM register
- SYStem.Option ETMFIX4 Use only every fourth ETM data package
- SYStem.Option EXEC EXEC signal can be used by bustrace
- SYStem.Option EXTBYPASS Switch off the fake TAP mechanism
- SYStem.Option FASTBREAKDETECTION Faster detection if core has halted
- SYStem.Option ICEBreakerETMFIXMarvell Lock on-chip breakpoints
- SYStem.Option ICEPICKONLY Only ICEPick registers accessible
- SYStem.Option IMASKASM Disable interrupts while single stepping
- SYStem.Option IMASKHLL Disable interrupts while HLL single stepping
- SYStem.Option INTDIS Disable all interrupts
- SYStem.Option IRQBREAKFIX Break bugfix by using IRQ
- SYStem.Option IntelSOC Debugging of an Intel SOC
- SYStem.Option KEYCODE Define key code to unsecure processor
- SYStem.Option L2Cache L2 cache used
- SYStem.Option L2CacheBase Define base address of L2 cache register
- SYStem.Option LOCKRES Go to "Test-Logic Reset" when locked
- SYStem.Option MEMORYHPROT Select memory-AP HPROT bits
- SYStem.Option MMUSPACES Enable multiple address spaces support
- SYStem.Option MonitorHoldoffTime Delay between monitor accesses
- SYStem.Option MPU Debugger ignores MPU access permission settings
- SYStem.Option MultiplesFIX No multiple loads/stores
- SYStem.Option NODATA No data connected to the trace
- SYStem.Option NOIRCHECK No JTAG instruction register check
- SYStem.Option NoPRCRReset Do not cause reset by PRCR
- SYStem.Option NoRunCheck No check of the running state
- SYStem.Option NoSecureFix Do not switch to secure mode
- SYStem.Option OVERLAY Enable overlay support
- SYStem.Option PALLADIUM Extend debugger timeout
- SYStem.Option PC Define address for dummy fetches
- SYStem.Option PROTECTION Sends an unsecure sequence to the core
- SYStem.Option PWRCHECK Check power and clock
- SYStem.Option PWRCHECKFIX Check power and clock
- SYStem.Option PWRDWN Allow power-down mode
- SYStem.Option PWRDWNRecover Mode to handle special power recovery
- SYStem.Option PWRDWNRecoverTimeOut Timeout for power recovery
- SYStem.Option PWROVR Specifies power override bit
- SYStem.Option ResBreak Halt the core after reset
- SYStem.Option ResetDetection Choose method to detect a target reset
- SYStem.Option RESTARTFIX Wait after core restart
- SYStem.Option RisingTDO Target outputs TDO on rising edge
- SYStem.Option ShowError Show data abort errors
- SYStem.Option SOFTLONG Use 32-bit access to set breakpoint
- SYStem.Option SOFTQUAD Use 64-bit access to set breakpoint
- SYStem.Option SOFTWORD Use 16-bit access to set breakpoint
- SYStem.Option SPLIT Access memory depending on CPSR
- SYStem.Option StandByTraceDelaytime Delay for activating trace after reset
- SYStem.Option STEPSOFT Use software breakpoints for ASM stepping
- SYStem.Option SYSPWRUPREQ Force system power
- SYStem.Option TIDBGEN Activate initialization for TI derivatives
- SYStem.Option TIETMFIX Bug fix for customer specific ASIC
- SYStem.Option TIDEMUXFIX Bug fix for customer specific ASIC
- SYStem.Option TraceStrobe Obsolete command
- SYStem.Option TRST Allow debugger to drive TRST
- SYStem.Option TURBO Speed up memory access
- SYStem.Option WaitReset Wait with JTAG activities after deasserting reset
- SYStem.Option ZoneSPACES Enable symbol management for ARM zones
- SYStem.RESetOut Assert nRESET/nSRST on JTAG connector
- SYStem.view Display SYStem window
- ARM Specific Benchmarking Commands
- ARM Specific TrOnchip Commands
- TrOnchip.A Programming the ICE breaker module
- TrOnchip.A.Value Define data selector
- TrOnchip.A.Size Define access size for data selector
- TrOnchip.A.CYcle Define access type
- TrOnchip.A.Address Define address selector
- TrOnchip.A.Trans Define access mode
- TrOnchip.A.Extern Define the use of EXTERN lines
- TrOnchip.AddressMask Define an address mask
- TrOnchip.ContextID Enable context ID comparison
- TrOnchip.CONVert Extend the breakpoint range
- TrOnchip.Mode Configure unit A and B
- TrOnchip.RESet Reset on-chip trigger settings
- TrOnchip.Set Set bits in the vector catch register
- TrOnchip.TEnable Define address selector for bus trace
- TrOnchip.TCYcle Define cycle type for bus trace
- TtrOnchip.VarCONVert Convert variable breakpoints
- TrOnchip.view Display on-chip trigger window
- CPU specific MMU Commands
- Target Adaption
- Support
- Products
ARM Debugger 90 ARM specific SYStem Commands
©1989-2014 Lauterbach GmbH
This option selects the value used for the HPROT bits in the Control Status Word (CSW) of an AXI Access
Port of a DAP, when using the AXI: memory class.
SYStem.Option BUGFIX Breakpoint bug fix
Default: OFF.
Breakpoint bug fix required on ARM7TDMI-S Rev2:
You need to activate this option when having an ARM7TDMI-S Rev2. The bug is fixed on Rev3 and
following. With this option activated and ARM7TDMIS selected as CPU type, we enable the software
breakpoint work around as described in the ARM errata of ARM7TDMI-S Rev2 (“consecutive breakpoint”
bug). Software breakpoints are set as undefined opcodes that cause the core to enter the undefined opcode
handler. The debugger tries to set a breakpoint at the undef vector (either software or on-chip). When a
breakpoint is reached the core will take the undefined exception and stop at the vector. The debugger
detects this state and displays the correct registers and cpu state. This work around is only suitable where
undefined instruction trap handling is not being used.
Breakpoint bug fix required on ARM946E-S Rev0, Rev1 and ARM966E-S Rev0, Rev1:
(This is a different bug fix as for the ARM7.) This option will automatically be activated by the TRACE32
software, since the core revision will be read out. On the above revisions the breakpoint code normally used
for software breakpoints behave wrong. Having this option active an undefined opcode is used together with
an on-chip comparator instead of the breakpoint code.
This option is available on ARM7 and on ARM9, but it has a different meaning.
SYStem.Option BUGFIXV4 Asynch. break bug fix for ARM7TDMI-S REV4
Default: OFF.
This option is available on ARM7. You need to activate this option when having an ARM7TDMI-S Rev4.
With this option activated, we replace an asynchronous break, e.g. caused by the “break” command, by a
break caused by an on-chip breakpoint range. If the bugfix is not activated when using an ARM7TDMI-S
Rev4, the application might be restarted at a wrong address.
Format: SYStem.Option BUGFIX [ON | OFF]
Format: SYStem.Option BUGFIXV4 [ON | OFF]