Specifications

ARM Debugger 4 1 A R M S p e c i f i c I m p l e m e n t a t i o n s
©1989-2014 Lauterbach GmbH
Example for a non-symmetric big.LITTLE configuration (1 Cortex-A15, 2 Cortex-A7):
Consequence for Debugging
The shown core numbers are extended by ‘b’ = ‘big’ or ‘l’ = ‘LITLLE’.
The core status (active or powered down) can be checked with CORE.SHOWACTIVE or in the state line of
the TRACE32 main window, where you can switch between the cores.
The debugger assumes that one core of the pair is inactive.
The OS awareness sees each pair as one virtual core.
The peripheral file respects the core type (Cortex-A15 or Cortex-A7).
Requirements for the Target Software
The routine (OS on target) which switches between the cores needs to take care of (copying) transferring the
on-chip debug settings to the core which wakes up.
This needs also to be done when waking up a core pair. In this case you copy the settings from an already
active core.
big.LITTLE MP
Another logical use-model is (‘MP’ = Multi-Processing). It allows both the big and the LITTLE core to be
powered on and to simultaneously execute code.
From the debuggers point of view, this is not a big.LITTLE system in the narrow sense. There are no pairs of
cores. It is handled like a normal multicore system but with mixed core types.
Therefore for the setup, we need SYStem.CPU CORTEXA15A7, but we use CORE.ASSIGN instead of
CORE.ASSIGN BIGLITTLE.
Example for a symmetric big.LITTLE MP configuration (2 Cortex-A15, 2 Cortex-A7):
SYStem.CPU CORTEXA15A7
SYStem.CONFIG CoreNumber 4.
CORE.ASSIGN BIGLITTLE 1. 2. NONE 4.
SYStem.CONFIG.COREDEBUG.Base <CA15_1> <CA7_2> <dummy_3> <CA7_4>
SYStem.CPU CORTEXA15A7
SYStem.CONFIG CoreNumber 4.
CORE.ASSIGN 1. 2. 3. 4.
SYStem.CONFIG.COREDEBUG.Base <CA15_1> <CA7_2> <CA15_3> <CA7_4>