Specifications

ARM Debugger 3 4 A R M S p e c i f i c I m p l e m e n t a t i o n s
©1989-2014 Lauterbach GmbH
Combinations of the classes are possible. Example: ’ZSR ’ accesses ARM code in secure, privileged mode.
To access a memory class write the class in front of the address. Example:
Normally there is no need to use the following memory classes: P, D, SP, UP, SR, ST, UR, UT, U, S, R, or T.
The memory class is set automatically depending on the setting of SYStem.Option DisMode.
The “User” memory classes are available if a DEBUG INTERFACE (LA-7701) is used for the ARM7.
The memory class ICE, C14 and ETM should only be used from very advanced users. Wrong usage may
cause unpredictable problems.
DAP, DAP2,
AHB,AHB2,
APB,APB2,
AXI,AXI2
Memory access via bus masters, so named Memory Access Ports
(MEM-AP), provided by a Debug Access Port (DAP). The DAP is a
CoreSight component mandatory on Cortex based devices.
Which bus master (MEM-AP) is used by which access class (e.g. AHB) is
defined by assigning a MEM-AP number to the access class:
SYStem.CONFIG DEBUGACCESSPORT <mem-ap#> -> “DAP”
SYStem.CONFIG AHBACCESSPORT <mem-ap#> -> “AHB”
SYStem.CONFIG APBACCESSPORT <mem-ap#> -> “APB”
SYStem.CONFIG AXIACCESSPORT <mem-ap#> -> “AXI”
You should assign the memory access port connected to an AHB (AHB
MEM-AP) to “AHB” access class, APB MEM-AP to “APB” access class
and AXI MEM-AP to “AXI” access class. “DAP” should get the memory
access port where the debug register can be found which typically is an
APB MEM-AP (AHB MEM-AP in case of a Cortex-M).
There is a second set of access classes (DAP2, AHB2, APB2, AXI2) and
configuration commands (e.g. SYStem.CONFIG
DAP2AHBACCESSPORT <mem-ap#>) available in case there are two
DAPs which needs to be controlled by the debugger.
VM Virtual Memory (memory on the debug system)
USR Access to Special Memory via User Defined Access Routines
E Run-time memory access
(see SYStem.CpuAccess and SYStem.MemAccess)
Data.dump NSD:0--3