Specifications
Table Of Contents
- ARM Debugger
- Brief Overview of Documents for New Users
- Warning
- Quick Start of the JTAG Debugger
- Troubleshooting
- FAQ
- Trace Extensions
- Symmetric Multiprocessing
- ARM Specific Implementations
- ARM specific SYStem Commands
- SYStem.BdmClock Define JTAG frequency
- SYStem.CLOCK Inform debugger about core clock
- SYStem.CONFIG Configure debugger according to target topology
- SYStem.CPU Select the used CPU
- SYStem.CpuAccess Run-time memory access (intrusive)
- SYStem.JtagClock Define JTAG frequency
- SYStem.LOCK Tristate the JTAG port
- SYStem.MemAccess Run-time memory access
- SYStem.Mode Establish the communication with the target
- SYStem.Option ABORTFIX Do not access 0x0-0x1f
- SYStem.Option AHBHPROT Select AHB-AP HPROT bits
- SYStem.Option AMBA Select AMBA bus mode
- SYStem.Option ASYNCBREAKFIX Asynchronous break bugfix
- SYStem.Option AXIACEEnable ACE enable flag of the AXI-AP
- SYStem.Option AXICACHEFLAGS Select AXI-AP CACHE bits
- SYStem.Option AXIHPROT Select AXI-AP HPROT bits
- SYStem.Option BUGFIX Breakpoint bug fix
- SYStem.Option BUGFIXV4 Asynch. break bug fix for ARM7TDMI-S REV4
- SYStem.Option BigEndian Define byte order (endianess)
- SYStem.Option BOOTMODE Define boot mode
- SYStem.Option CINV Invalidate the cache after memory modification
- SYStem.Option CFLUSH FLUSH the cache before step/go
- SYStem.Option CacheParam Define external cache
- SYStem.Option DACR Debugger ignores DACR access permission settings
- SYStem.Option DAPNOIRCHECK No DAP instruction register check
- SYStem.Option DAPREMAP Rearrange DAP memory map
- SYStem.Option DBGACK DBGACK active on debugger memory accesses
- SYStem.Option DBGNOPWRDWN DSCR bit 9 will be set when in debug mode
- SYStem.Option DBGUNLOCK Unlock debug register via OSLAR
- SYStem.Option DCDIRTY Bugfix for erroneously cleared dirty bits
- SYStem.Option DCFREEZE Disable data cache linefill in debug mode
- SYStem.Option DIAG Activate more data.log messages
- SYStem.Option DisMode Define disassembler mode
- SYStem.Option DynVector Dynamic trap vector interpretation
- SYStem.Option EnReset Allow the debugger to drive nRESET/nSRST
- SYStem.Option ETBFIXMarvell Read out on-chip trace data
- SYStem.Option ETMFIX Shift data of ETM scan chain by one
- SYStem.Option ETMFIXWO Bugfix for write-only ETM register
- SYStem.Option ETMFIX4 Use only every fourth ETM data package
- SYStem.Option EXEC EXEC signal can be used by bustrace
- SYStem.Option EXTBYPASS Switch off the fake TAP mechanism
- SYStem.Option FASTBREAKDETECTION Faster detection if core has halted
- SYStem.Option ICEBreakerETMFIXMarvell Lock on-chip breakpoints
- SYStem.Option ICEPICKONLY Only ICEPick registers accessible
- SYStem.Option IMASKASM Disable interrupts while single stepping
- SYStem.Option IMASKHLL Disable interrupts while HLL single stepping
- SYStem.Option INTDIS Disable all interrupts
- SYStem.Option IRQBREAKFIX Break bugfix by using IRQ
- SYStem.Option IntelSOC Debugging of an Intel SOC
- SYStem.Option KEYCODE Define key code to unsecure processor
- SYStem.Option L2Cache L2 cache used
- SYStem.Option L2CacheBase Define base address of L2 cache register
- SYStem.Option LOCKRES Go to "Test-Logic Reset" when locked
- SYStem.Option MEMORYHPROT Select memory-AP HPROT bits
- SYStem.Option MMUSPACES Enable multiple address spaces support
- SYStem.Option MonitorHoldoffTime Delay between monitor accesses
- SYStem.Option MPU Debugger ignores MPU access permission settings
- SYStem.Option MultiplesFIX No multiple loads/stores
- SYStem.Option NODATA No data connected to the trace
- SYStem.Option NOIRCHECK No JTAG instruction register check
- SYStem.Option NoPRCRReset Do not cause reset by PRCR
- SYStem.Option NoRunCheck No check of the running state
- SYStem.Option NoSecureFix Do not switch to secure mode
- SYStem.Option OVERLAY Enable overlay support
- SYStem.Option PALLADIUM Extend debugger timeout
- SYStem.Option PC Define address for dummy fetches
- SYStem.Option PROTECTION Sends an unsecure sequence to the core
- SYStem.Option PWRCHECK Check power and clock
- SYStem.Option PWRCHECKFIX Check power and clock
- SYStem.Option PWRDWN Allow power-down mode
- SYStem.Option PWRDWNRecover Mode to handle special power recovery
- SYStem.Option PWRDWNRecoverTimeOut Timeout for power recovery
- SYStem.Option PWROVR Specifies power override bit
- SYStem.Option ResBreak Halt the core after reset
- SYStem.Option ResetDetection Choose method to detect a target reset
- SYStem.Option RESTARTFIX Wait after core restart
- SYStem.Option RisingTDO Target outputs TDO on rising edge
- SYStem.Option ShowError Show data abort errors
- SYStem.Option SOFTLONG Use 32-bit access to set breakpoint
- SYStem.Option SOFTQUAD Use 64-bit access to set breakpoint
- SYStem.Option SOFTWORD Use 16-bit access to set breakpoint
- SYStem.Option SPLIT Access memory depending on CPSR
- SYStem.Option StandByTraceDelaytime Delay for activating trace after reset
- SYStem.Option STEPSOFT Use software breakpoints for ASM stepping
- SYStem.Option SYSPWRUPREQ Force system power
- SYStem.Option TIDBGEN Activate initialization for TI derivatives
- SYStem.Option TIETMFIX Bug fix for customer specific ASIC
- SYStem.Option TIDEMUXFIX Bug fix for customer specific ASIC
- SYStem.Option TraceStrobe Obsolete command
- SYStem.Option TRST Allow debugger to drive TRST
- SYStem.Option TURBO Speed up memory access
- SYStem.Option WaitReset Wait with JTAG activities after deasserting reset
- SYStem.Option ZoneSPACES Enable symbol management for ARM zones
- SYStem.RESetOut Assert nRESET/nSRST on JTAG connector
- SYStem.view Display SYStem window
- ARM Specific Benchmarking Commands
- ARM Specific TrOnchip Commands
- TrOnchip.A Programming the ICE breaker module
- TrOnchip.A.Value Define data selector
- TrOnchip.A.Size Define access size for data selector
- TrOnchip.A.CYcle Define access type
- TrOnchip.A.Address Define address selector
- TrOnchip.A.Trans Define access mode
- TrOnchip.A.Extern Define the use of EXTERN lines
- TrOnchip.AddressMask Define an address mask
- TrOnchip.ContextID Enable context ID comparison
- TrOnchip.CONVert Extend the breakpoint range
- TrOnchip.Mode Configure unit A and B
- TrOnchip.RESet Reset on-chip trigger settings
- TrOnchip.Set Set bits in the vector catch register
- TrOnchip.TEnable Define address selector for bus trace
- TrOnchip.TCYcle Define cycle type for bus trace
- TtrOnchip.VarCONVert Convert variable breakpoints
- TrOnchip.view Display on-chip trigger window
- CPU specific MMU Commands
- Target Adaption
- Support
- Products
ARM Debugger 154 Support
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PCD80720 YES YES YES YES
PCD80721 YES YES YES YES
PCD80725 YES YES YES YES
PCD80727 YES YES YES YES
PCD80728 YES YES YES YES
PCF26002 YES YES YES
PCF26003 YES YES YES
PCF87750 YES YES YES
PCI2010 YES YES YES
PCI3610 YES YES YES
PCI3620 YES YES YES
PCI3700 YES YES YES
PCI3800 YES YES YES
PCI5110 YES YES YES
PCI9501 YES YES YES
PH21101 YES YES YES
PMB7754 YES YES YES
PS7500FE YES YES YES
PUC3030A YES YES YES
PUC303XA YES YES YES
S3C3400A YES YES YES
S3C3400X YES YES YES
S3C3410X YES YES YES
S3C44A0A YES YES YES
S3C44B0X YES YES YES
S3C4510B YES YES YES
S3C4520A YES YES YES
S3C4530A YES YES YES
S3C4610D YES YES YES
S3C4620D YES YES YES
S3C4640X YES YES YES
S3C4650D YES YES YES
S3C46C0 YES YES YES
S3C46M0X YES YES YES
S3C4909A YES YES YES
S3C49F9X YES YES YES
S3F401F YES YES YES
S3F441FX YES YES YES
S3F460H YES YES YES
S5N8946 YES YES YES
S5N8947 YES YES YES
CPU
ICE
FIRE
ICD
DEBUG
ICD
MONITOR
ICD
TRACE
POWER
INTEGRATOR
INSTRUCTION
SIMULATOR