Specifications

ARM Debugger 126 ARM Specific Benchmarking Commands
©1989-2014 Lauterbach GmbH
On ARM1136 there are two separate counters PMN0 and PMN1 available. The <mode> parameter of the
BMC.PMNx-command selects the events which should be counted.
OFF Switch off the performance monitor.
INST The selected counter counts executed instructions.
BINST Counts executed branch instructions.
BMIS Counts branches which were mispredicted by the core (for static) or prefetch
unit (for dynamic) branch prediction. A branch misprediction causes the pipeline
to be flushed, and the correct instruction to be fetched.
PC Counts changes of the PC by the program e.g. as in a MOV or LDR instruction
with PC as destination.
ICMISS Counts instruction cache misses which requires a instruction fetch from the
external memory.
ITLBMISS Counts misses of the instruction MicroTLB.
ISTALL ISTALL increments the counter by 1 for every cycle the condition is valid. The
CPU is stalled when the instruction buffer cannot deliver an instruction. This
happens as a result of an instruction cache miss or an instruction MicroTLB
miss.
DACCESS DACCESS is incremented by 1 for every nonsequential data access, regardless
of whether or not the item is cached or not.
DCACHE DCACHE is incremented for each access to the data cache.
DCMISS DCMISS counts for missing data in the data cache.
DTBLMISS Counts misses in the data MicroTLB.
DSTALL In a data dependency conflict the CPU is stalled. DSTALL increments the
counter by one for every cycle the stall persists.
DFULL If the pipeline of load store unit is full, the counter will be incremented by one for
each clock the condition is met.
DCWB Data cache write back occurs for each half line of four words that are written
back from cache to memory.
WBDRAIN Write buffer drains force all buffered data writes to be written to external
memory. WBDRAIN will count all that drains which are done because of a data
synchronization barrier or strongly ordered operations.
TBLMISS Counts main TLB misses.