ARM Debugger TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents ...................................................................................................................... ICD In-Circuit Debugger ................................................................................................................ Processor Architecture Manuals .............................................................................................. ARM/CORTEX/XSCALE .................
Semihosting 28 SVC (SWI) Emulation Mode 28 DCC Communication Mode (DCC = Debug Communication Channel) 30 Runtime Measurement 31 Coprocessors 32 Access Classes 33 TrustZone Technology 35 Debug Permission 35 Checking Debug Permission 36 Checking Secure State 36 Changing the Secure State from within TRACE32 36 Accessing Memory 36 Accessing Coprocessor CP15 Register 37 Accessing Cache and TLB Contents 37 Breakpoints and Vector Catch Register 37 Large Physical Address Extension (LPA
SYStem.Option AMBA SYStem.Option ASYNCBREAKFIX Select AMBA bus mode 88 Asynchronous break bugfix 89 ACE enable flag of the AXI-AP 89 SYStem.Option AXICACHEFLAGS Select AXI-AP CACHE bits 89 SYStem.Option AXIHPROT Select AXI-AP HPROT bits 89 SYStem.Option AXIACEEnable SYStem.Option BUGFIX SYStem.Option BUGFIXV4 Breakpoint bug fix 90 Asynch. break bug fix for ARM7TDMI-S REV4 90 Define byte order (endianess) 91 Define boot mode 91 SYStem.Option BigEndian SYStem.Option BOOTMODE SYStem.
SYStem.Option MMUSPACES Enable multiple address spaces support 103 SYStem.Option MonitorHoldoffTime SYStem.Option MPU Delay between monitor accesses 103 Debugger ignores MPU access permission settings 103 No multiple loads/stores 104 No data connected to the trace 104 SYStem.Option MultiplesFIX SYStem.Option NODATA No JTAG instruction register check 105 SYStem.Option NoPRCRReset SYStem.Option NOIRCHECK Do not cause reset by PRCR 105 SYStem.
BMC.MODE Define the operating mode of the benchmark counter BMC.PMNx Configure the performance monitor Functions 124 125 129 BMC.PRESCALER Prescale the measured cycles 129 Calibrate the benchmark counter 129 ARM Specific TrOnchip Commands ................................................................................ 130 BMC.TARA TrOnchip.A Programming the ICE breaker module 130 Define data selector 130 Define access size for data selector 130 Define access type 131 TrOnchip.A.
Compilers 173 Realtime Operation Systems 174 3rd Party Tool Integrations 176 Products .............................................................................................................................
ARM Debugger Version 11-Nov-2014 07-Aug-14 Added new access classes, see “Coprocessors” and “Access Classes”. 30-Jun-14 TrBus.Out and TrBus.Set were moved to general_ref_t.pdf. 26-Jun-14 New command SYStem.Option ZoneSPACES. 13-Mar-14 Added section “big.LITTLE”, revised sections “TrustZone Technology”, “Large Physical Address Extension (LPAE)”, and “Virtualization Extension, Hypervisor”. 05-Nov-13 Updated the BMC.EXPORT description.
- Choose Help menu > Processor Architecture Manual. • “RTOS Debugger” (rtos_.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware debugging. • This manual does not cover the Cortex-A5x (ARMv8) cores, please refer to ”ARMv8-A Debugger” (debugger_armv8a.pdf) if you are using this processor architecture.
Quick Start of the JTAG Debugger Starting up the debugger is done as follows: 1. Reset the debugger. RESet The RESet command ensures that no debugger setting remains from a former debug session. All settings get their default value. RESet is not required if you start the debug session directly after booting the TRACE32 development tool. RESet does not reset the target. 2. Select the chip or core you intend to debug. SYStem.CPU Based on the selected chip the debugger sets the SYStem.
A start sequence example is shown below. This sequence can be written to an ASCII file (script file) and executed with the command DO . WinCLEAR ; Clear all windows SYStem.CPU ARM940T ; Select the core type MAP.BOnchip 0x100000++0xfffff ; Specify where FLASH/ROM is SYStem.Up ; Reset the target and enter debug mode Data.LOAD armle.axf ; Load the application Register.Set pc main ; Set the PC to function main Register.Set r13 0x8000 ; Set the stack pointer to address 8000 PER.
Troubleshooting Communication between Debugger and Processor can not be established Typically the SYStem.Up command is the first command of a debug session where communication with the target is required. If you receive error messages like “debug port fail” or “debug port time out” while executing this command this may have the reasons below. “target processor in reset” is just a follow-up error message. Open the “AREA” window to see all error messages.
FAQ ARM Debugging via VPN The debugger is accessed via Internet/VPN and the performance is very slow. What can be done to improve debug performance? The main cause for bad debug performance via Internet or VPN are low data throughput and high latency. The ways to improve performance by the debugger are limited: in practice scripts, use "SCREEN.OFF" at the beginning of the script and "SCREEN.ON" at the end. "SCREEN.OFF" will turn off screen updates. Please note that if your program stops (e.g.
Setting a Software Breakpoint fails What can be the reasons why setting a software breakpoint fails? Setting a software breakpoint can fail when the target HW is not able to implement the wanted breakpoint. Possible reasons: The wanted breakpoint needs special features that are only possible to realize by the trigger unit inside the controller. Example: Read, write and access (Read/Write) breakpoints ("type" in Break.Set window). Breakpoints with checking in real-time for data-values ("Data").
Unstable Data Why do I have flickering data in some windows? Please make sure that the TURBO mode is off (SYStem.Option TURBO OFF). Another setting that may solve the problem is the reduction of the JTAG frequency (SYStem.JtagClock 5 MHz). ARM7 Setting a Software Breakpoint fails What can be the reasons why setting a software-breakpoint fails? Setting a software breakpoint can fail when the target HW is not able to realize the wanted breakpoint.
JANUS No information available ARM9 Setting a Software Breakpoint fails What can be the reasons why setting a software-breakpoint fails? Setting a software breakpoint can fail when the target HW is not able to realize the wanted breakpoint. Possible reasons: • The wanted breakpoint needs special features that are only possible to realize by the trigger unit inside the controller. Example: Read, Write and Access (Read/Write) breakpoints ("type" in Break.Set window).
ARM10 Arm Dongle Modifications for ARM Dongle ARM11 Setting a Software Breakpoint fails What can be the reasons why setting a software-breakpoint fails? Setting a software breakpoint can fail when the target HW is not able to realize the wanted breakpoint. Possible reasons: • The wanted breakpoint needs special features that are only possible to realize by the trigger unit inside the controller. Example: Read, Write and Access (Read/Write) breakpoints ("type" in Break.Set window).
Cortex-A/-R No information available XSCALE Setting a Software Breakpoint fails What can be the reasons why setting a software-breakpoint fails? Setting a software breakpoint can fail when the target HW is not able to realize the wanted breakpoint. Possible reasons: • The wanted breakpoint needs special features that are only possible to realize by the trigger unit inside the controller. Example: Read, Write and Access (Read/Write) breakpoints ("type" in Break.Set window).
Trace Extensions There are two types of trace extensions available on the ARM: • ARM-ETM: an Embedded Trace Macrocell or Program Trace Macrocell is integrated into the core. The Embedded Trace Macrocell provides program and data flow information plus trigger and filter features. The Program Trace Macrocell provide similar features but no data trace. The TRACE32 does not distinguish between ETM and PTM. The ETM command group is used for both.
Symmetric Multiprocessing A multi-core system used for Asymmetric Multiprocessing (AMP) has specialized cores which are used for specific tasks. To debug such a system you need to open separate TRACE32 graphical user interfaces (GUI) one for each core. On each GUI you debug the application which is assigned to this core and will never be executed on an other core. The GUIs can be synchronized regarding program start and halt in order to debug the cores interaction.
ARM Specific Implementations Breakpoints Software Breakpoints If a software breakpoint is used, the original code at the breakpoint location is patched by a breakpoint code. While software breakpoints are used one of the two ICE breaker units is programmed with the breakpoint code (on ARM7 and ARM9, except ARM9E variants). This means whenever a software breakpoint is set only one ICE unit breakpoint is remaining for other purposes. There is no restriction in the number of software breakpoints.
Overview • On-chip breakpoints: Total amount of available on-chip breakpoints. • Instruction breakpoints: Number of on-chip breakpoints that can be used to set program breakpoints into ROM/FLASH/EPROM. • Read/Write breakpoints: Number of on-chip breakpoints that can be used as Read or Write breakpoints.
Hardware Breakpoints (Bus Trace only) When a Preprocessor for ARM7 family is used, hardware breakpoints are available to filter the trace information. Refer to TrOnchip.TEnable for more information. If a hardware breakpoint is used the resources to set the breakpoint are provided by the TRACE32 development tool.
Example for Standard Breakpoints Assume you have a target with • FLASH from 0x0--0xfffff • RAM from 0x100000--0x11ffff The command to configure TRACE32 correctly for this configuration is: Map.BOnchip 0x0--0xfffff The following standard breakpoint combinations are possible. 1. 2. 3. 4. Unlimited breakpoints in RAM and one breakpoint in ROM/FLASH Break.Set 0x100000 /Program ; Software breakpoint 1 Break.Set 0x101000 /Program ; Software breakpoint 2 Break.
5. One breakpoint in ROM/FLASH and one breakpoint on a read or write access Break.Set 0x100 /Program ; On-chip breakpoint 1 Break.
Complex Breakpoints To use the advanced features of the ICE breaker unit the TrOnchip command group is possible. These commands provide full access to both ICE breaker units called A and B in the TRACE32 system. For an example of complex breakpoint usage please refer to the chapter TrOnchip Example. Most features can also be used by setting advanced breakpoints (e.g. task selective breakpoints, exclude breakpoints).
Trigger A bidirectional trigger system allows the following two events: • trigger an external system (e.g. logic analyzer) if the program execution is stopped. • stop the program execution if an external trigger is asserted. For more information refer to the TrBus command. If a DEBUG INTERFACE (LA-7701) is used the trigger system has the following restrictions: • After starting the application there is a delay until the trigger system is working.
Virtual Terminal The command TERM opens a terminal window which allows to communicate with the ARM core over the Debug Communications Channel (DCC). All data received from the comms channel are displayed and all data inputs to this window are sent to the comms channel. Communication occurs byte wide or up to four bytes per transfer. The four bytes ASCII mode (DCC4A) does not allow to transfer the byte 00. Each nonzero byte of the 32 bit word is a character in this mode.
Semihosting Semihosting is a technique for an application program running on an ARM processor to communicate with the host computer of the debugger. This way the application can use the I/O facilities of the host computer like keyboard input, screen output, and file I/O. This is especially useful if the target platform does not yet provide these I/O facilities or in order to output additional debug information in printf() style.
TERM.HEAPINFO defines the system stack and heap location. The C library reads these memory parameters by a SYS_HEAPINFO semihosting call and uses them for initialization. An example can be found in demo/arm/etc/semihosting_arm_emulation/swisoft_x.cmm. + " ! " ( " , - .
DCC Communication Mode (DCC = Debug Communication Channel) A semihosting exception handler will be called by the SVC (SWI) exception. It uses the Debug Communication Channel based on the JTAG interface to communicate with the host. The target application will not be stopped, but the semihosting exception handler needs to be loaded or linked to the application. The Cortex-M does not provide a DCC, therefore this mode can not be used. This mode is enabled by TERM.METHOD DCC3 and by opening a TERM.
In case the ARM library for semihosting is not used, you can alternatively use the native TRACE32 format for the semihosting requests. Then the SWI handler (t32swi.c) is not required. You can send the requests directly via DCC. Find examples and source codes in demo/arm/etc/semihosting_trace32_dcc.
Coprocessors The following coprocessors can be accessed if available in the processor: Coprocessor 14. Please refer to the chapter Virtual Terminal and to your ARM documentation for details. On Cortex-A and Cortex-R the debug register can be accessed by ’C14’ access class and the address is the address offset in the debug register block divided by 4.
Access Classes The following ARM specific access classes are available.
DAP, DAP2, AHB,AHB2, APB,APB2, AXI,AXI2 Memory access via bus masters, so named Memory Access Ports (MEM-AP), provided by a Debug Access Port (DAP). The DAP is a CoreSight component mandatory on Cortex based devices. Which bus master (MEM-AP) is used by which access class (e.g. AHB) is defined by assigning a MEM-AP number to the access class: SYStem.CONFIG DEBUGACCESSPORT -> “DAP” SYStem.CONFIG AHBACCESSPORT -> “AHB” SYStem.CONFIG APBACCESSPORT -> “APB” SYStem.
TrustZone Technology The Cortex-A and ARM1176 processor integrate ARM’s TrustZone technology, a hardware security extension, to facilitate the development of secure applications. It splits the computing environment into two isolated worlds. Most of the code runs in the ‘non-secure’ world, whereas trusted code runs in the ‘secure’ world. There are core operations that allow you to switch between the secure and non-secure world. For switching purposes, TrustZone introduces a new secure ‘monitor’ mode.
Checking Debug Permission The DBGDSCR (Debug Status and Control Register) bit 16 shows the signal level of SPIDEN. In the SDER (Secure Debug Enable Register) you can see the SUIDEN flag assuming you are in the secure state which allows reading the SDER register. Checking Secure State In the peripheral file, the DBGDSCR register bit 18 (NS) shows the current secure state. You can also see it in the Register.view window if you scroll down a bit.
Accessing Coprocessor CP15 Register The peripheral file and ‘C15:’ access class will show you the CP15 register bank of the secure mode the core is currently in. When you try to access registers in non-secure world which are accessible in secure world only, the debugger will show you ‘????????’. You can force to see the other bank by using access class “ZC15:” for secure, “NC15:” for non-secure respectively.
Large Physical Address Extension (LPAE) LPAE is an optional extension for the ARMv7-AR architecture. It allows physical addresses above 32-bit. The instructions still use 32-bit addresses, but the extended memory management unit can map the address within a 40-bit physical memory range. virtual address (32-bit) --> extended MMU --> physical address (40-bit) It is for example implemented on Cortex-A7 and Cortex-A15.
Virtualization Extension, Hypervisor The ‘Virtualization Extension’ is an optional extension in ARMv7-A. It can for example be found on Cortex-A7 and Cortex-A15. It adds a ‘Hypervisor’ processor mode used to switch between different guest operating systems. The extension assumes LPAE and TrustZone. It adds a second stage address translation. virtual addr. (32-bit) --> MMU --> intermediate physical addr. (40-bit) --> MMU_2nd --> physical addr.
big.LITTLE ARM big.LITTLE processing is an energy savings method where high-performance cores get paired together in a cache-coherent combination. Software execution will dynamically be transitioned between these cores depending on performance needs. measure workload big task toggle CPU #0 measure workload Scheduler task big toggle CPU #1 LITTLE . . .
Example for a non-symmetric big.LITTLE configuration (1 Cortex-A15, 2 Cortex-A7): SYStem.CPU CORTEXA15A7 SYStem.CONFIG CoreNumber 4. CORE.ASSIGN BIGLITTLE 1. 2. NONE 4. SYStem.CONFIG.COREDEBUG.Base Consequence for Debugging The shown core numbers are extended by ‘b’ = ‘big’ or ‘l’ = ‘LITLLE’. The core status (active or powered down) can be checked with CORE.SHOWACTIVE or in the state line of the TRACE32 main window, where you can switch between the cores.
ARM specific SYStem Commands SYStem.BdmClock Define JTAG frequency Obsolete command syntax. It has the same effect as SYStem.JtagClock. Use SYStem.JtagClock instead. SYStem.CLOCK Format: Inform debugger about core clock SYStem.CLOCK The command informs the debugger about the core clock frequency. The information is used for analysis functions where the core frequency needs to be known. This command is only available if the debugger is used as front end for virtual prototyping.
SYStem.CONFIG Configure debugger according to target topology Format: SYStem.CONFIG SYStem.
ETBIRPRE IRPOST IRPRE NEXTDRPOST NEXTDRPRE NEXTIRPOST NEXTIRPRE RTPDRPOST RTPDRPRE RTPIRPOST RTPIRPRE Slave [ON | OFF] TAPState TCKLevel TriState [ON | OFF] : (Multitap) CFGCONNECT DAP2TAP DAPTAP DEBUGTAP ETBTAP MULTITAP [NONE | IcepickA | IcepickB | IcepickC | IcepickD | IcepickBB | IcepickBC | IcepickCC | IcepickDD | STCLTAP1 | STCLTAP2 | STCLTAP3 | MSMTAP
: (Components) ADTF.Base ADTF.RESET AET.Base AET.RESET BMC.Base BMC.RESET CMI.Base CMI.RESET CMI.TraceID COREDEBUG.Base COREDEBUG.RESET CTI.Base CTI.Config [NONE | ARMV1 | ARMPostInit | OMAP3 | TMS570 | CortexV1 | QV1] CTI.RESET DRM.Base DRM.
DTM.RESET DTM.Type [None | Generic] DWT.Base
DWT.RESET EPM.Base EPM.RESET ETB2AXI.Base ETB2AXI.RESET ETB.ATBSource ETB.Base ETB.RESET ETB.Size ETF.ATBSource ETF.Base ETF.RESET ETM.Base ETM.RESET ETR.ATBSource ETR.Base ETR.RESET FUNNEL.ATBSource FUNNEL.Base FUNNEL.Name FUNNEL.RESET HSM.Base HSM.RESET HTM.Base HTM.RESET ICE.Base ICE.RESET ITM.TPIU.Base
TPIU.TIEPMBASE
TIICEBASE TIOCPBASE TIOCPTYPE TIPMIBASE TISCBASE TISTMBASE TPIUBASE TPIUFUNNELBASE TRACEETBFUNNELPORT TRACEFUNNELPORT TRACETPIUFUNNELPORT view The SYStem.CONFIG commands inform the debugger about the available on-chip debug and trace components and how to access them. This is a common description of the SYStem.CONFIG command group for the ARM, CevaX, TI DSP and Hexagon debugger. describing the “Debugport” CJTAGFLAGS Activates bug fixes for “cJTAG” implementations. Bit 0: Disable scanning of cJTAG ID. Bit 1: Target has no “keeper”. Bit 2: Inverted meaning of SREDGE register. Bit 3: Old command opcodes. Bit 4: Unlock cJTAG via APFC register. Default: 0 CJTAGTCA Selects the TCA (TAP Controller Address) to address a device in a cJTAG Star-2 configuration. The Star-2 configuration requires a unique TCA for each device on the debug port.
CORE The command helps to identify debug and trace resources which are commonly used by different cores. The command might be required in a multicore environment if you use multiple debugger instances (multiple TRACE32 GUIs) to simultaneously debug different cores on the same target system. Because of the default setting of this command debugger#1: =1 =1 debugger#2: =1 =2 ...
DEBUGPORTTYPE [JTAG | SWD | CJTAG | CJTAGSWD] It specifies the used debug port type “JTAG”, “SWD”, “CJTAG”, “CJTAG-SWD”. It assumes the selected type is supported by the target. Default: JTAG. What is NIDnT? NIDnT is an acronym for “Narrow Interface for Debug and Test”. NIDnT is a standard from the MIPI Alliance, which defines how to reuse the pins of an existing interface (like for example a microSD card interface) as a debug and test interface.
NIDNTTRSTTORST [ON | OFF] Usually TRACE32 requires that the system reset line of a target system is low active and has a pull-up on the target system. This is how the system reset line is usually implemented on regular ARM-based targets. When connecting via NIDnT (e.g. a microSD card slot) to the target system, the reset line might not include a pull-up on the target system. To circumvent problems, TRACE32 allows to drive the target reset line via the TRST signal of an ARM debug cable.
SWDPTargetSel Device address in case of a multidrop serial wire debug port. Default: 0. TriState [ON | OFF] TriState has to be used if several debug cables are connected to a common JTAG port. TAPState and TCKLevel define the TAP state and TCK level which is selected when the debugger switches to tristate mode. Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-down resistor, other trigger inputs needs to be kept in inactive state. Default: OFF.
describing the “JTAG” scan chain and signal behavior With the JTAG interface you can access a Test Access Port controller (TAP) which has implemented a state machine to provide a mechanism to read and write data to an Instruction Register (IR) and a Data Register (DR) in the TAP. The JTAG interface will be controlled by 5 signals: nTRST(reset), TCK (clock), TMS (state machine control), TDI (data input), TDO (data output).
Slave [ON | OFF] If several debugger share the same debug port, all except one must have this option active. JTAG: Only one debugger - the “master” - is allowed to control the signals nTRST and nSRST (nRESET). The other debugger need to have Slave=OFF. Default: OFF; ON if CORE=... >1 in config file (e.g. config.t32). For CortexM: Please check also SYStem.Option DISableSOFTRES [ON | OFF] TAPState This is the state of the TAP controller when the debugger switches to tristate mode.
TAP types: Core TAP providing access to the debug register of the core you intend to debug. -> DRPOST, DRPRE, IRPOST, IRPRE. DAP (Debug Access Port) TAP providing access to the debug register of the core you intend to debug. It might be needed additionally to a Core TAP if the DAP is only used to access memory and not to access the core debug register. -> DAPDRPOST, DAPDRPRE, DAPIRPOST, DAPIRPRE. DAP2 (Debug Access Port) TAP in case you need to access a second DAP to reach other memory locations.
©1989-2014 Lauterbach GmbH ARM Debugger 57 ARM specific SYStem Commands
describing a system level TAP “Multitap” A “Multitap” is a system level or chip level test access port (TAP) in a JTAG scan chain. It can for example provide functions to re-configure the JTAG chain or view and control power, clock, reset and security of different chip components.
DEBUGTAP Specifies the TAP number which needs to be activated to get the core TAP in the JTAG chain. E.g. ARM11 TAP if you intend to debug an ARM11. Used if MULTITAP=Icepickx. ETBTAP Specifies the TAP number which needs to be activated to get the ETB TAP in the JTAG chain. Used if MULTITAP=Icepickx. ETB = Embedded Trace Buffer.
configuring a CoreSight Debug Access Port “DAP” A Debug Access Port (DAP) is a CoreSight module from ARM which provides access via its debugport (JTAG, cJTAG, SWD) to: 1. Different memory busses (AHB, APB, AXI). This is especially important if the on-chip debug register needs to be accessed this way. You can access the memory buses by using certain access classes with the debugger commands: “AHB:”, “APB:”, “AXI:, “DAP”, “E:”. The interface to these buses is called Memory Access Port (MEM-AP). 2.
Debug Access Port (DAP) Debugger 0 Memory Access Port (MEM-AP) Debug Port JTAG or cJTAG or SWD System Memory Debug Bus (APB) Chip System Bus (AHB) Example: Debug Register Trace Register 1 Memory Access Port (MEM-AP) ROM Table 0 JTAG 2 JTAG Access Port (JTAG-AP) 7 JTAG AHBACCESSPORT 0 MEMORYACCESSPORT 0 APBACCESSPORT 1 DEBUGACCESSPORT 1 JTAGACCESSPORT 2 ARM9 COREJTAGPORT 7 AHBACCESSPORT DAP access port number (0-255) which shall be used for “AHB:” access class. Default: =0.
DAP2AHBACCESSPORT DAP2 access port number (0-255) which shall be used for “AHB2:” access class. Default: =0. DAP2APBACCESSPORT DAP2 access port number (0-255) which shall be used for “APB2:” access class. Default: =1. DAP2AXIACCESSPORT DAP2 access port number (0-255) which shall be used for “AXI2:” access class. Default: port not available DAP2DEBUGACCESSPORT DAP2 access port number (0-255) where the debug register can be found (typically on APB).
DAP2APBNAME APB bus transactor name that shall be used for “APB2:” access class. DAP2AXINAME AXI bus transactor name that shall be used for “AXI2:” access class. DAP2DEBUGBUSNAME APB bus transactor name identifying the bus where the debug register can be found. Used for “DAP2:” access class. DAP2MEMORYBUSNAME AHB bus transactor name identifying the bus where system memory can be accessed even during runtime. Used for “E:” access class while running, assuming “SYStem.
describing debug and trace “Components” In the “Components” folder in the “SYStem.CONFIG.state” window you can comfortably add the debug and trace components your chip includes and which you intend to use with the debugger’s help. Each configuration can be done by a command in a script file as well. Then you do not need to enter everything again on the next debug session.
You can have several of the following components: CMI, ETB, ETF, ETR, FUNNEL, STM. Example: FUNNEL1, FUNNEL2, FUNNEL3,... The
parameter can be just an address (e.g. 0x80001000) or you can add the access class in front (e.g. AHB:0x80001000). Without access class it gets the command specific default access class which is “EDAP:” in most cases. Example: Core ETM Core ETM 0 1 FUNNEL 0 FUNNEL STM TPIU 7 SYStem.CONFIG.COREDEBUG.Base 0x80010000 0x80012000 SYStem.CONFIG.BMC.... .ATBSource Specify for components collecting trace information from where the trace data are coming from. This way you inform the debugger about the interconnection of different trace components on a common trace bus. You need to specify the “... .Base ” or other attributes that define the amount of existing peripheral modules before you can describe the interconnection by “... .ATBSource ”.
Example: Four cores with ETM modules. SYStem.CONFIG ETM.Base 0x1000 0x2000 0x3000 0x4000 SYStem.CONFIG FUNNEL1.ATBSource ETM.0 0 ETM.1 1 ETM.2 2 ETM.3 3 "...2" of "ETM.2" indicates it is the third ETM module which has the base address 0x3000. The indices of a list are 0, 1, 2, 3,... If the numbering is accelerating, starting from 0, without gaps, like the example above then you can shorten it to SYStem.CONFIG FUNNEL1.ATBSource ETM Example: Four cores, each having an ETM module and an ETB module. SYStem.
... .TraceID Identifies from which component the trace packet is coming from. Components which produce trace information (trace sources) for a common trace stream have a selectable “.TraceID ”. If you miss this SYStem.CONFIG command for a certain trace source (e.g. ETM) then there is a dedicated command group for this component where you can select the ID (ETM.TraceID ). The default setting is typically fine because the debugger uses different default TraceIDs for different components.
OCP.Type Specifies the type of the OCP module. The is just a number which you need to figure out in the chip documentation. RTP.PerBase PERBASE specifies the base address of the core peripheral registers which accesses shall be traced. PERBASE is needed for the RAM Trace Port (RTP) which is available on some derivatives from Texas Instruments. The trace packages include only relative addresses to PERBASE and RAMBASE. RTP.
COREDEBUG.Base
COREDEBUG.RESET Core Debug Register - ARM debug register, e.g. on Cortex-A/R Some cores do not have a fix location for their debug register used to control the core. In this case it is essential to specify its location before you can connect by e.g. SYStem.Up. CTI.Base CTI.Config [NONE | ARMV1 | ARMPostInit | OMAP3 | TMS570 | CortexV1 | QV1] CTI.ETM.Base
ETM.RESET Embedded Trace Macrocell (ETM) - ARM CoreSight module Program Trace Macrocell (PTM) - ARM CoreSight module Trace source providing information about program flow and data accesses of a core. The ETM commands will be used even for PTM. ETR.ATBSource ETR.Base ETR.RESET Embedded Trace Router (ETR) - ARM CoreSight module Enables trace to be routed over an AXI bus to system memory or to any other AXI slave. FUNNEL.ATBSource FUNNEL.Base FUNNEL.RTP.Base
RTP.PerBase RTP.RamBase RTP.RESET RAM Trace Port (RTP) - Texas Instruments Trace source delivering trace data about memory interface usage. SC.Base SC.RESET SC.TraceID Statistic Collector (SC) - Texas Instruments Trace source delivering statistic data about bus traffic to a system trace module. STM.Base STM.Mode [NONE | XTIv2 | SDTI | STP | STP64 | STPv2] STM.RESET STM. which are “Deprecated” In the last years the chips and its debug and trace architecture became much more complex. Especially the CoreSight trace components and their interconnection on a common trace bus required a reform of our commands. The new commands can deal even with complex structures. ... BASE This command informs the debugger about the start address of the register block of the component. And this way it notifies the existence of the component.
... PORT Informs the debugger about which trace source is connected to which input port of which funnel. A CoreSight trace funnel provides 8 input ports (port 0-7) to combine the data of various trace sources to a common trace stream. Example: SYStem.CONFIG STMFUNNEL2PORT 3 Meaning: The System Trace Module (STM) is connected to input port #3 on FUNNEL2. On a SMP debug session some of these commands can have a list of parameter.
DTMCONFIG [ON | OFF] Informs the debugger that a customer proprietary Data Trace Message (DTM) module is available. This causes the debugger to consider this source when capturing common trace data. Trace data from this module will be recorded and can be accessed later but the unknown DTM module itself will not be controlled by the debugger. FILLDRZERO [ON | OFF] This changes the bypass data pattern for other TAPs in a multiTAP JTAG chain. It changes the pattern from all “1” to all “0”.
ETBBASE
ETB1.Base ETBFUNNELBASE FUNNEL4.Base ETFBASE ETF1.Base ETMBASE ETM.Base ETMETBFUNNELPORT FUNNEL4.ATBSource ETM (1) ETMFUNNEL2PORT FUNNEL2.ATBSource ETM (1) ETMFUNNELPORT FUNNEL1.ATBSource ETM (1) ETMTPIUFUNNELPORT FUNNEL3.ATBSource ETM (1) FILLDRZERO [ON | OFF] CHIPDRPRE 0 CHIPDRPOST 0 CHIPDRLENGTH CHIPDRPATTERN.TIADTFBASE
ADTF.Base TIDRMBASE DRM.Base TIEPMBASE EPM.Base TIICEBASE ICE.Base TIOCPBASE OCP.Base TIOCPTYPE OCP.Type TIPMIBASE PMI.Base TISCBASE SC.Base TISTMBASE STM1.Base STM1.Mode STP STM1.Type TI TPIUBASE TPIU.Base TPIUFUNNELBASE FUNNEL3.Default selection: • ARM7TDMI if the JTAG Debugger for ARM7 is used. • ARM9TDMI if the JTAG Debugger for ARM9 is used. • JANUS2 if the JTAG Debugger for JANUS is used. • ARM1020E if the JTAG Debugger for ARM10 is used. • ARM1136J if the JTAG Debugger for ARM11 is used. • CORTEXA8 if the JTAG Debugger for Cortex-A is used. • CORTEXM3 if the JTAG Debugger for Cortex-M is used. SYStem.CpuAccess Format: Run-time memory access (intrusive) SYStem.
SYStem.JtagClock Define JTAG frequency Format: SYStem.JtagClock [ | RTCK | ARTCK | CTCK | CRTCK ] 4 kHz…100 MHz 1250000. | 2500000. | 5000000. | 10000000. (on obsolete ICD hardware) Default frequency: 10 MHz. Selects the JTAG port frequency (TCK) used by the debugger to communicate with the processor. This influences e.g. the download speed.
ARTCK: Accelerated method to control the JTAG clock by the RTCK signal (Accelerated Returned TCK). RTCK mode allows theoretical frequencies up to 1/6 (ARM7, ARM9) or 1/8 (ARM11) of the processor clock. For designs using a very low processor clock we offer a different mode (ARTCK) which does not work as recommended by ARM and might not work on all target systems. In ARTCK mode the debugger uses a fixed JTAG frequency for TCK, independent of the RTCK signal.
SYStem.LOCK Format: Tristate the JTAG port SYStem.LOCK [ON | OFF] Default: OFF. If the system is locked no access to the JTAG port will be performed by the debugger. While locked the JTAG connector of the debugger is tristated. The intention of the lock command is for example to give JTAG access to another tool. The process can also be automated, see SYStem.CONFIG TriState. It must be ensured that the state of the ARM core JTAG state machine remains unchanged while the system is locked.
SYStem.MemAccess Run-time memory access Format: SYStem.MemAccess : Cerberus CPU DAP NEXUS TSMON3 TSMON PTMON3 PTMON QMON UDMON3 UDMON RealMON TrkMON GdbMON Denied Default: Denied. If SYStem.MemAccess is not Denied, it is possible to read from memory, to write to memory and to set software breakpoints while the CPU is executing the program. This requires one of the following monitors. Cerberus The memory access is done through an Infineon proprietary Cerberus module.
TSMON3 TSMON TSMON uses a data format which shall not be used anymore. It still works for compatibility reasons. TSMON3 shall be used. A run-time memory access is done via a Time Sharing Monitor. The application is responsible for calling the monitor code periodically. The call is typically included in a periodic interrupt or in the idle task of the kernel. See the example in the directory demo/arm/etc/runtime_memory_access.
PTMON3 PTMON PTMON uses a data format which shall not be used anymore. It still works for compatibility reasons. PTMON3 shall be used. A run-time memory access is done via a Pulse Triggered Monitor. Whenever the debugger wants to perform a memory access while the program is running, the debugger generates a trigger for the trigger bus. If the trigger bus is configured appropriate (TrBus), this trigger is output via the TRIGGER connector of the TRACE32 development tool.
UDMON3 UDMON UDMON uses a data format which shall not be used anymore. It still works for compatibility reasons. UDMON3 shall be used. A run-time memory access is done via a Usermode Debug Monitor. The application is responsible for calling the monitor code periodically. The call is typically included in a periodic interrupt or in the idle task of the kernel. For runtime memory access UDMON3 behaves exactly as TSMON3.
SYStem.Mode Establish the communication with the target Format: SYStem.Mode : Down NoDebug Go Attach StandBy Up Prepare Down Disables the debugger (default). The state of the CPU remains unchanged. The JTAG port is tristated. NoDebug Disables the debugger. The state of the CPU remains unchanged. The JTAG port is tristated. Go Resets the target and enables the debugger and start the program execution. Program execution can be stopped by the break command or external trigger.
Example of a CoreSight based System The pictures give an idea which MultiCore option informs about which part of the system.
SYStem.Option ABORTFIX Format: Do not access 0x0-0x1f SYStem.Option ABORTFIX [ON | OFF] Default: OFF. Work around for a special customer configuration. It suppresses all debugger accesses to memory area 0x0-0x1f. This feature is only available on ARM7 family. SYStem.Option AHBHPROT Format: Select AHB-AP HPROT bits SYStem.
SYStem.Option ASYNCBREAKFIX Format: Asynchronous break bugfix SYStem.Option ASYNCBREAKFIX [ON | OFF] This option is required for Cortex-A9, Cortex-A9MPCore r0p0, r0p1, r1p0, r1p1. Default: OFF. CPSR.T and CPSR.J bits can be corrupted on an asynchronous break. The fix causes the debugger to replace the asynchronous break by a synchronous break via breakpoint register. Breaks via external DBGRQ signal e.g. from CTI still fail and may not be used. SYStem.
This option selects the value used for the HPROT bits in the Control Status Word (CSW) of an AXI Access Port of a DAP, when using the AXI: memory class. SYStem.Option BUGFIX Format: Breakpoint bug fix SYStem.Option BUGFIX [ON | OFF] Default: OFF. Breakpoint bug fix required on ARM7TDMI-S Rev2: You need to activate this option when having an ARM7TDMI-S Rev2. The bug is fixed on Rev3 and following.
There is no known work around to secure correct behavior of the external DBGRQ input and a program halt caused by an ETM trigger condition. Therefore do not use these features on an ARM7TDMI-S Rev4. SYStem.Option BigEndian Format: Define byte order (endianess) SYStem.Option BigEndian [ON | OFF] Default: OFF. This option selects the byte ordering mechanism.
SYStem.Option CINV Format: Invalidate the cache after memory modification SYStem.Option CINV [ON | OFF] Default: OFF. If this option is ON the cache is invalidated after memory modifications even when memory is modified by the EPROM Simulator (ESI). This is necessary to maintain software breakpoint consistency. SYStem.Option CFLUSH Format: FLUSH the cache before step/go SYStem.Option CFLUSH [ON | OFF] Default: ON.
SYStem.Option DACR Format: Debugger ignores DACR access permission settings SYStem.Option DACR [ON | OFF] Default: OFF. Derivatives having a Domain Access Control Registers (DACR) do not allow the debugger to access memory if the location does not have the appropriate access permission. If this option is activated, the debugger temporarily modifies the access permission to get access to any memory location. SYStem.Option DAPNOIRCHECK Format: No DAP instruction register check SYStem.
Disabling of this option may be useful for triggering on memory accesses from debug mode (only useful for hardware developers). This option is not available on the ARM10. SYStem.Option DBGNOPWRDWNDSCR bit 9 will be set when in debug mode Format: SYStem.Option DBGNOPWRDWN [ON | OFF] Default: OFF. If this option is on DSCR[9] will be set while the core is in debug mode and cleared while the user application is running. SYStem.Option PWRDWN will be ignored. This option is normally not useful.
This is a work around for a chip bug which erroneously clears the dirty bits of a data cache line if there is any write-through forced by the debugger in this line. When the option is active the debugger does not use writethrough mode in general. It only forces write through on a program memory write. This option is only available on the ARM1176, Cortex-R, Cortex-A. SYStem.Option DCFREEZE Format: Disable data cache linefill in debug mode SYStem.Option DCFREEZE [ON | OFF] Default: ON.
SYStem.Option DisMode Define disassembler mode Format: SYStem.Option DisMode
SYStem.Option DynVector Format: Dynamic trap vector interpretation SYStem.Option DynVector [ON | OFF] This option is only available on XScale. Default: OFF. If this option is ON and a trap occurs the trap vector is read from memory and the trap vector is executed out of the memory. The vector tables have be overloaded by the debugger to place the debug vector instead of the reset vector.
SYStem.Option ETMFIX Format: Shift data of ETM scan chain by one SYStem.Option ETMFIX [ON | OFF] Default: OFF. Bug fix for ETM7 implementations showing a wrong shift behavior. The ETM register data will be shifted by one bit otherwise. This feature is only available on the ARM7 family. SYStem.Option ETMFIXWO Format: Bugfix for write-only ETM register SYStem.Option ETMFIXWO [ON | OFF] Default: OFF. Bug fix for a customer device where ETM registers can not be read.
SYStem.Option EXTBYPASS Format: Switch off the fake TAP mechanism SYStem.Option EXTBYPASS [ON | OFF] Default: ON. Bugfix for DB8500 V1. It allows you to switch off the fake TAP mechanism of the modem. SYStem.Option FASTBREAKDETECTION Faster detection if core has halted Format: SYStem.Option FASTBREAKDETECTION [ON | OFF] Default: OFF. It advises the debugger to do a permanent polling via JTAG to check if the core has halted.
SYStem.Option ICEPICKONLY Format: Only ICEPick registers accessible SYStem.Option ICEPICKONLY [ON | OFF] Default: OFF. Obsolete command. Used in TRACE32 versions from September 2004 until May 2005, has no effect anymore. This option caused the debugger to switch into a mode where certain debug register, which are only available on certain processor derivatives, had been accessible even when the processor was powered down. Newer TRACE32 versions allow the access at every time.
SYStem.Option INTDIS Format: Disable all interrupts SYStem.Option INTDIS [ON | OFF] Default: OFF. If this option is ON all interrupts to the ARM core are disabled. This option is not available on the ARM10. SYStem.Option IRQBREAKFIX Format: Break bugfix by using IRQ SYStem.Option IRQBREAKFIX
The bug shows up on Cortex-A9, Cortex-A9MPCore r0p0, r0p1, r1p0, r1p1. Default: 0 = OFF. CPSR.T and CPSR.J bits can be corrupted on an asynchronous break.Some processors have a security feature and require a key to unsecure the processor in order to allow debugging. The processor will use the specified key on the next debugger start-up (e.g. SYStem.Up) and forgets it immediately. For the next start-up the keycode must be specified again. This option is available on ARM9. SYStem.Option L2Cache Format: L2 cache used SYStem.Option L2Cache [ON | OFF] Default: OFF, means no L2 cache is used.
SYStem.Option MEMORYHPROT Format: Select memory-AP HPROT bits SYStem.Option MEMORYHPROT Default: 0 This option selects the value used for the HPROT bits in the Control Status Word (CSW) of an Memory Access Port of a DAP, when using the E: memory class. SYStem.Option MMUSPACES Format: Enable multiple address spaces support SYStem.Option MMUSPACES [ON | OFF] SYStem.Option MMU [ON | OFF] (deprecated) Default: OFF. Enables the usage of the MMU to support multiple address spaces.
Derivatives having a memory protection unit do not allow the debugger to access memory if the location does not have the appropriate access permission. If this option is activated, the debugger temporarily modifies the access permission to get access to the memory location. SYStem.Option MultiplesFIX Format: No multiple loads/stores SYStem.Option MultiplesFIX [ON | OFF] Default: OFF. Bug fix for derivatives (e.g. ARM946 V1.
SYStem.Option NOIRCHECK Format: No JTAG instruction register check SYStem.Option NOIRCHECK [ON | OFF] Default: OFF. Bug fix for derivatives which do not return the correct pattern on a JTAG instruction register (IR) scan. When activated the returned pattern will not be checked by the debugger. On ARM7 also the check of the return pattern on a scan chain selection is disabled. This option is only available on ARM7 and ARM9. The option is automatically activated when using SYStem.Option TURBO. SYStem.
SYStem.Option NoSecureFix Format: Do not switch to secure mode SYStem.Option NoSecureFix [ON | OFF] Default: OFF. This is a bugfix for customer specific devices which do not allow the debugger to temporarily switch to secure mode while the application is in non-secure mode. SYStem.Option OVERLAY Format: Enable overlay support SYStem.Option OVERLAY [ON | OFF | WithOVS] Default: OFF. ON: Activates the overlay extension and extends the address scheme of the debugger with a 16 bit virtual OverlayID.
The debugger uses longer timeouts as might be needed when used on a chip emulation system like the Palladium from Cadence. SYStem.Option PC Format: Define address for dummy fetches SYStem.Option PC Default address: 0 After each load or store operation from debug mode the ARM core makes some instruction fetches from memory. These fetches are not necessary for the debugger, but it is not possible to suppress them. This option allows to specify the base address of these fetches.
SYStem.Option PWRCHECKFIX Format: Check power and clock SYStem.Option PWRCHECKFIX [ON | OFF] Default: OFF. Fix for a certain chip bug: It uses the OSLK bit instead of the SPD bit of the PRSR register to detect power down. This option is only available on Cortex-R, Cortex-A. SYStem.Option PWRDWN Format: Allow power-down mode SYStem.Option PWRDWN [ON | OFF] Default: OFF.
This option is only available on ARM9. SYStem.Option PWRDWNRecoverTimeOut Format: Timeout for power recovery SYStem.Option PWRDWNRecoverTimeOut
sequence is only possible while nTRST is inactive. In the following figure the marked time between the deassertion of reset and the entry into debug mode is the time of this JTAG sequence plus a time delay selectable by SYStem.Option WaitReset (default = 3 msec). nSRST nTRST CPU State reset running debug If nTRST is available and not connected to nRESET/nSRST it is possible to force the CPU directly after reset (without cycles) into debug mode.
SYStem.Option RESTARTFIX Format: Wait after core restart SYStem.Option RESTARTFIX [ON | OFF] Default: OFF. Bug fix for a certain customer derivative. When activated the debugger keeps the JTAG state machine on every restart for 10 µs in Run-Test/Idle state before the JTAG communication will be continued. This option is available on ARM7 and will be ignored on other debuggers. SYStem.Option RisingTDO Format: Target outputs TDO on rising edge SYStem.Option RisingTDO [ON | OFF] Default: OFF.
SYStem.Option SOFTLONG Format: Use 32-bit access to set breakpoint SYStem.Option SOFTLONG [ON | OFF] Default: OFF. This option instructs the debugger to use 32-bit accesses to patch the software breakpoint code. SYStem.Option SOFTQUAD Format: Use 64-bit access to set breakpoint SYStem.Option SOFTQUAD [ON | OFF] Default: OFF. Activate this option if software breakpoints should be written by 64-bit accesses. This was implemented in order not to corrupt ECC. SYStem.
SYStem.Option StandByTraceDelaytime Delay for activating trace after reset Format: SYStem.Option StandByTraceDelaytime Default: 0. Only when standby mode is active you can specify a time delay where the debugger waits after reset is deasserted before it activates the trace. This option is available on ARM9 only. SYStem.Option STEPSOFT Format: Use software breakpoints for ASM stepping SYStem.Option STEPSOFT [ON | OFF] Default: OFF.
If this option is active the debugger sends a special initialization sequence, which is required for some derivatives from Texas Instruments (TI) to enable the on-chip debug support. When a TI CPU type (e.g. “OMAP1510”) is selected, this option is automatically set. This option is only available on ARM9. SYStem.Option TIETMFIX Format: Bug fix for customer specific ASIC SYStem.Option TIETMFIX [ON | OFF] SYStem.Option TIDEMUXFIX Format: Bug fix for customer specific ASIC SYStem.
SYStem.Option TraceStrobe Format: Obsolete command SYStem.Option TraceStrobe [CE | OE | CE+OE | STR | STR-] This command is obsolete. SYStem.Option TRST Format: Allow debugger to drive TRST SYStem.Option TRST [ON | OFF] Default: ON. If this option is disabled the nTRST line is never asserted by the debugger (permanent high). Instead five consecutive TCK pulses with TMS high are asserted to reset the TAP controller which have the same effect. SYStem.
SYStem.Option WaitReset Format: Wait with JTAG activities after deasserting reset SYStem.Option WaitReset [ON | OFF |
SYStem.Option ZoneSPACES Format: Enable symbol management for ARM zones SYStem.Option ZoneSPACES [ON | OFF] Default: OFF The SYStem.Option ZoneSPACES command is relevant if an ARM CPU with TrustZone or VirtualizationExtension is debugged. In these ARM CPUs, the processor has two or more CPU operation modes called: • Nonsecure mode • Secure mode • Hypervisor mode Within TRACE32, these CPU operation modes are referred to as zones.
SYStem.Option ZoneSPACES ON If the ZoneSPACES option is enabled (ON), TRACE32 enforces any memory address specified in a TRACE32 command to have an access class which clearly indicates to which zone it belongs. If an address specified in a command is not clearly attributed to N: Z: or H:, the access class of the current PC context is used to complete the addresses’ access class. Every loaded symbol is attributed to either nonsecure (N:), secure (Z:) or hypervisor (H:) zone.
Example 2 - Symbolic memory access: ; dump the address on symbol swapper_pg_dir which belongs ; to the nonsecure symbol set "vmlinux" we have loaded above: Data.Dump swapper_pg_dir ; This will automatically use access class N: for the memory access, ; even if the CPU is currently not in nonsecure mode. Example 3 - Deleting Zone-specific Symbols: To delete a complete symbol set belonging to a specific zone, e.g.
In such a setup with hypervisor and guest OS, it is possible to load both the hypervisor symbols to H: and all OS-related symbols to N: A TRACE32 OS awareness can be loaded in TRACE32 to support the work with the OS in the guest system. This is done as follows: 1. 2. Configure the OS awareness as for a non-virtualized system. See: - ”Training Linux Debugging” (training_rtos_linux.pdf) - TASK.CONFIG command Additionally set the default access class of the OS awareness to the nonsecure zone: TASK.
Example setup for a guest OS and a hypervisor: In this example, the hypervisor is configured to run in zone H: and a Linux kernel with OS awareness as current guest OS in zone N: SYStem.Option ZoneSPACES ON ; within the OS awareness we need SpaceID to separate address spaces of ; different processes / tasks SYStem.Option MMUSPACES ON ; here we let the target system boot the hypervisor. The hypervisor will ; set up the guest and boot linux on the guest system. ... ; load the hypervisor symbols Data.LOAD.
SYStem.RESetOut Format: Assert nRESET/nSRST on JTAG connector SYStem.RESetOut If possible (nRESET/nSRST is open collector), this command asserts the nRESET/nSRST line on the JTAG connector. While the CPU is in debug mode this function will be ignored. Use the SYStem.Up command if you want to reset the CPU in debug mode. SYStem.view Format: Display SYStem window SYStem.view Display the SYStem window for ARM.
ARM Specific Benchmarking Commands The BMC (BenchMark Counter) commands provide control of the on-chip performance monitor unit (PMU). The PMU consists of a group of counters that can be configured to count certain events in order to get statistics on the operation of the processor and the memory system. The counters of Cortex-A/-R cores can be read at run-time. The counters of ARM11 cores can only be read while the target application is halted.
BMC.MODE Define the operating mode of the benchmark counter Format: BMC.MODE : OFF ICACHE DCACHE SYSIF CLOCK TIME This command only applies to some ARM9 based derivatives from Texas Instruments. The Benchmark Counter - short BMC - is a hardware counter. It collects information about the throughput of the target processor, like instruction or data cache misses. This information may be helpful in finding bottlenecks and tuning the application. OFF Switch off the benchmark counter.
BMC.PMNx Configure the performance monitor Format: BMC.PMN0 | PMN1 : OFF INST BINST BMIS PC ICMISS ITLBMISS ISTALL DACCESS DCACHE DCMISS DTBLMISS DSTALL DFULL DCWB WBDRAIN TLBMISS EMEM ETMEXTOUT0 ETMEXTOUT1 Delta Echo CLOCK TIME NONE PMN0/PMN1 PMN1/PMN0 PMN0/PMNC PMN1/PMNC The command is available on ARM1136, ARM1176 and Cortex-A8. This description applies to ARM1136. All available modes are described in detail in the technical reference guide of the ARM cores.
On ARM1136 there are two separate counters PMN0 and PMN1 available. The parameter of the BMC.PMNx-command selects the events which should be counted. OFF Switch off the performance monitor. INST The selected counter counts executed instructions. BINST Counts executed branch instructions. BMIS Counts branches which were mispredicted by the core (for static) or prefetch unit (for dynamic) branch prediction.
EMEM Incremented for each explicit external data access. That includes cache refills, non-cachable and write-through access. It does not include instruction cache fills or data write backs. ETMEXTOUT 0 The counter is incremented, if the ETMEXTOUT0-signal is asserted for a cycle. The ETM can be programmed to rise that signal on behalf / as result of certain events, like a counter overflow or an address compare. EMTEXTOUT 1 The counter is incremented, if the ETMEXTOUT1-signal is asserted for a cycle.
To count for branches taken, in relation to mispredicted branches, use the following commands: BMC.RESet ; Reset the BMC settings BMC.state ; Display the BMC window BMC.PMN0 BINST ; Set the first (PMN0) performance counter ; to count all taken branches BMC.PMN1 BMIS ; Set the second (PMN1) performance counter ; to mispredicted branches BMC.PMN0 PMN1/PMN0 ; Calculate the ratio between branches ; taken and branches mispredicted Go sieve ; Go to the function sieve BMC.
Functions BMC.COUNTER() Reads out the benchmark counter PMNx. BMC.PRESCALER Format: Prescale the measured cycles BMC.PRESCALER [ON | OFF] If ON, the cycle counter register, which counts for the cpu cycles which is used to measure the elapsed time, will be divided (prescaled) by 64. The display of the time will be corrected accordingly. BMC.TARA Format: Calibrate the benchmark counter BMC.
ARM Specific TrOnchip Commands The TrOnchip command provides low level access to the on-chip debug register. TrOnchip.A Programming the ICE breaker module Available for ARM7 and ARM9 family. TrOnchip.A.Value Format: Define data selector TrOnchip.A.Value | TrOnchip.B.Value | Defines the two data selectors of ICE breaker as hex or binary mask (x means don't care).
TrOnchip.A.CYcle Define access type Format: TrOnchip.A.CYcle TrOnchip.B.CYcle : OFF Read Write Access Execute Defines on which cycle the ICE breaker stops the program execution. OFF Cycle type doesn't matter. Read Stop the program execution on a read access. Write Stop the program execution on a write access. Access Stop the program execution on a read or write access. Execute Stop the program execution on an instruction is executed. Available for ARM7 and ARM9 family.
TrOnchip.A.Address Define address selector Format: TrOnchip.A.Address TrOnchip.B.Address : OFF Alpha Beta Charly The address/range for an address selector can not be defined directly. Set an breakpoint of the type Alpha, Beta or Charly to the address/range. Break.Set 1000 /Alpha TrOnchip.A.Address Alpha ; set an Alpha breakpoint to 1000 ; use Alpha breakpoint as address ; selector for the unit A Var.Break.Set flags[3] /Beta TrOnchip.B.
TrOnchip.A.Extern Define the use of EXTERN lines Format: TrOnchip.A.Extern TrOnchip.B.Extern : OFF Low High Defines if the EXTERN lines are considered by unit A or unit B. Available for ARM7 and ARM9 family. TrOnchip.AddressMask Format: Define an address mask TrOnchip.AddressMask | TrOnchip.ContextID Format: Enable context ID comparison TrOnchip.
If TrOnchip.Convert is set to ON (default) and a breakpoint is set to a range, this range is extended to the next possible bit mask. The result is, that in most cases a bigger address range is marked by the specified breakpoint. This can be easily controlled by the Data.View command. If TrOnchip.Convert is set to OFF, the debugger will only accept breakpoints which exactly fit to the on-chip breakpoint hardware. This setting affects all on-chip breakpoints. TrOnchip.
TrOnchip.Set Format: Set bits in the vector catch register TrOnchip.Set StepVector [ON | OFF] ARM9, ARM11 also: [FIQ | IRQ | DABORT | PABORT | SWI | UNDEF | RESET] Devices having TrustZone (ARM1176, Cortex-A) additionally: [NFIQ | NIRQ | NDABORT | NPABORT | NSWI | NUNDEF | SFIQ | SIRQ | SDABORT | SPABORT | SSWI | SUNDEF | SRESET | MAFIC | MIRQ | MDABORT | MPABORT | MSWI] Devices having a Hypervisor mode (e.g.
TrOnchip.TEnable Define address selector for bus trace Format: TrOnchip.TEnable : ALL Alpha Beta Charly Delta Echo Define a filter for the trace. The Preprocessor for the ARM7 family (bus trace) provides 1 address comparator, that is implemented as a comparator (bit mask). Since this comparator is provided by the TRACE32 development tools, it is listed as a Hardware Breakpoint. ; sample only entries to the function sieve Break.Set sieve /Charly TrOnchip.TEnable Charly TrOnchip.
TrOnchip.TCYcle Define cycle type for bus trace Format: TrOnchip.TCYcle : ANY Read Write Access Fetch Soft Defines the cycle type for the bus trace address selector. ANY Cycle type doesn't matter. Read Record only read accesses. Write Record only write accesses. Access Record only data accesses. Fetch Record only instruction fetches. Soft Not used now.
TtrOnchip.VarCONVert Format: Convert variable breakpoints TrOnchip.VarCONVert [ON | OFF] The ICE-breaker does not provide resources to set an on-chip breakpoint to an address range. Only bit masks can be used to mark a memory range with a breakpoint. If TrOnchip.VarCONVert is set to ON and a breakpoint is set to a scalar variable then it is converted into a single address breakpoint. If TrOnchip.VarCONVert is set to OFF variable breakpoints will be set to an address range covering the whole variable.
CPU specific MMU Commands MMU.DUMP Display MMU table Format: MMU.DUMP
[ | | | ] MMU..dump (deprecated) : PageTable KernelPageTable TaskPageTable and CPU specific tables Displays the contents of the CPU specific MMU translation table. • If called without parameters, the complete table will be displayed.CPU specific tables: ITLB Displays the contents of the Instruction Translation Lookaside Buffer. DTLB Displays the contents of the Data Translation Lookaside Buffer. TLB0 Displays the contents of the Translation Lookaside Buffer 0. TLB1 Displays the contents of the Translation Lookaside Buffer 1. NonSecurePageTable Displays the translation table used if the CPU is in nonsecure mode and in privilege level PL0 or PL1. This is the table pointed to by MMU registers TTBR0 and TTBR1 in nonsecure mode.
Description of columns in the TLB dump window Logical Logical address. Physical Physical address. Vmid Virtual machine ID. Asid Address space ID. Glb Global flag. Sec Non-secure identifier for physical address. idx Index of the TLB entry. pagesize Page size. Hyp Hypervisor entry flag. V Valid flag. L Locked flag. I Inner shareability flag. O Outer shareability flag. M Indicates if the line was brought in when MMU was enabled.
MMU.List Display MMU table Format: MMU.List [
[ | ]] MMU..List (deprecated) : PageTable KernelPageTable TaskPageTable Lists the address translation of the CPU specific MMU table. If called without address or range parameters, the complete table will be displayed. If called without a table specifier, this command shows the debugger internal translation table. See TRANSlation.List.CPU specific tables: NonSecurePageTable Displays the translation table used if the CPU is in nonsecure mode and in privilege level PL0 or PL1. This is the table pointed to by MMU registers TTBR0 and TTBR1 in nonsecure mode. This option is only visible if the CPU has the TrustZone and/or Virtualization Extension. This option is only enabled if Exception levels EL0 or EL1 use Aarch32 mode. SecurePageTable Displays the translation table used if the CPU is in secure mode.
PageTable Load the current MMU address translation of the CPU. This command reads all tables the CPU currently used for MMU translation, and copies the address translation into the debugger internal translation table. KernelPageTable Load the MMU translation table of the kernel. If specified with the MMU.FORMAT command, this command reads the table of the kernel and copies its address translation into the debugger internal translation table.
Target Adaption Probe Cables For debugging two kind of probe cable can be used to connect the debugger to the target: “Debug Cable” and “CombiProbe” The CombiProbe is mainly used on Cortex-M derivatives or in case a system trace port is available because it includes besides the debug interface a 4 bit wide trace port which is sufficient for Cortex-M program trace or for system trace. For off-chip program and data trace an additional trace probe cable “Preprocessor” is needed.
CombiProbe Adaption for ARM CombiProbe: See http://www.lauterbach.com/adarmcombi.html. The CombiProbe will always be delivered with 10-pin, 20-pin, 34-pin connectors. The CombiProbe can not detect which one is used. If you use the trace of the CombiProbe you need to inform about the used connector because the trace signals can be at different locations: SYStem.CONFIG CONNECTOR [MIPI34 | MIPI20T].
Support Available Tools AD6522 AD6526 AD6528 AD6529 AD6532 ADUC7020 ADUC7021 ADUC7022 ADUC7023 ADUC7024 ADUC7025 ADUC7026 ADUC7027 ADUC7028 ADUC7029 ADUC7030 ADUC7032 ADUC7033 ADUC7034 ADUC7036 ADUC7039 ADUC7060 ADUC7061 ADUC7121 ADUC7122 ADUC7124 ADUC7128 ADUC7129 ADUC7229 ARM710T ARM710T-AMBA YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES
YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD MONITOR YES ICD DEBUG FIRE ICE CPU ARM720T ARM720T-AMBA ARM740T ARM740T-AMB
INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE CPU AT91SAM7A2 AT91SAM7A3 AT91SAM7L128 AT91SAM7L64 AT91SAM7S128 AT91SAM7S256 AT91SAM7S3
INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE CPU CSM5000 CSM5200 CX81210 CX81400 D5205 D5313 D5314 EASYCAN1 EASYCAN2 EASYCAN4 EP7209 EP7211
YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES
YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE CPU LPC2364 LPC2365 LPC2366 LP
YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE CPU ML67Q5300 ML70511LA ML7051LA MN1A7T0200 MODEM MSM3000 MSM3100
YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE CPU PCD80720 PCD80721 PCD80725 PCD80727 PCD80728 PCF26002 PCF26003 PCF8775
YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE CPU SC100 SC110 SIRFSTARII SJA2020 SOCLITE+ ST30F7XXA ST30F7XXC ST30F7XX
INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE CPU TMS470R1VC336A TMS470R1VC338 TMS470R1VC346A TMS470R1VC348 TMS470R1VC688 TMS470R1VF288 TMS47
YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG 88AP128 88AP162 88AP166 88AP168 88E6208 88E6218 88F5082 88F5180N 88F5181 88F5181L 88F5182 88F5281 88F6082 88F6180 88F6183 88F6183
YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE CPU AAEC-2000 AM1707 AM1808 AM181
INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE CPU CX22491 CX22492 CX22496 CX82100 DB5500 DIGICOLOR-OA980 DRX401 DRX402 DRX403 DRX404 DRX4
YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE CPU EPXA1 EPXA10 EPXA4 ERTEC200 E
YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE CPU LPC3152 LPC
YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD
YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE
INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE CPU TMS320C6A8143 TMS320C6A8147 TMS320C6A8148 TMS320C6A8167 TMS320C6A8168 TMS320DA828 TMS320DA830 TMS320DM335 TMS320DM355 TMS320DM357 TMS320DM365 TMS320DM6441 TMS320DM6443 TMS320DM6446 TMS320DM6467 TMS320DM8147 TMS320DM8148 TMS320DM8165 TMS320DM8166 TMS32
ARM1020E ARM1022E ARM1026EJ-S YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR POWER INTEGRATOR ICD TRACE ICD MONITOR ICD DEBUG FIRE ICE CPU ARM10 YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG 8
YES YES YES YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE CPU MXC91231 MXC91321 MXC91323 MXC91331 OMAP2420 OMAP2430 OMAP2431 OMAPV2230 S3C6400 S3C6410 SP2603 SP2606 SP2612 SP2704 SP2716 STA2064 STA2065 STA2164 STA2165 YES YES YES YES YES YES YES YES YES YES YES YES YES
YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG 66AK2H06 66AK2H12 A9500 A95
YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES
YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE
YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE CPU RM46L852-
YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ICD TRACE ICD DEBUG FIRE ICE CPU TMS320DM81
ICD TRACE YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES INSTRUCTION SIMULATOR ICD MONITOR YES YES YES YES YES YES YES YES YES YES POWER INTEGRATOR ICD DEBUG FIRE ICE CPU VF31xR VF32xR VF3xx VF4xx VF51xR VF52xR VF5xx VF6xx VF7xx ZYNQ-7000 YES YES YES YES YES YES YES YES YES YES ©1989-2014 Lauterbach GmbH ARM Debugger 172 Support
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Products Product Information ARM7 OrderNo Code Text LA-7746 JTAG Debugger for ARM7 20 Pin Connector (ICD) JTAG-ARM7-20 supports ARM7 (0.4 V - 5 V) supports 5-pin standard JTAG, cJTAG and Serial Wire Debug Port includes software for Windows, Linux and MacOSX requires Power Debug Module cJTAG and SerialWire Debug require Power Debug Interface USB 2.0/USB 3.0, Power Debug Ethernet, PowerTrace or Power Debug II LA-7746A JTAG Debugger License for ARM7 Add.
OrderNo Code Text LA-3770 ARM Converter ARM-20 to MIPI-10/20/34 CONV-ARM20/MIPI34 Converter to connect a Debug Cable to 10/20/34 pin connectors specified by MIPI.
ARM9 OrderNo Code Text LA-7742 JTAG Debugger for ARM9 (ICD) JTAG-ARM9 supports ARM9 (0.4 V - 5 V) supports 5-pin standard JTAG, cJTAG and Serial Wire Debug Port includes software for Windows, Linux and MacOSX requires Power Debug Module cJTAG and Serial Wire Debug require Power Debug Interface USB 2.0/USB 3.0, Power Debug Ethernet, PowerTrace or Power Debug II LA-7742A JTAG Debugger License for ARM9 Add.
OrderNo Code Text LA-7742X JTAG Debugger Extension for ARM9 JTAG-ARM9-X supports ARM9 Extension applicable to the following debug cables (purchased separately): for LA-7744 (JTAG Debugger for ARM10) for LA-7746 (JTAG Debugger for ARM7) for LA-7762 (JTAG Debugger for XScale) for LA-7765 (JTAG Debugger for ARM11) for LA-7843 (JTAG Debugger for Cortex-A/-R (ARMv7)) for LA-7844 (JTAG Debugger for Cortex-M) requires a valid software guarantee or a valid software license key please add the serial number of t
ARM10 OrderNo Code Text LA-7744 JTAG Debugger for ARM10 (ICD) JTAG-ARM10 supports ARM10 (0.4 V - 5 V) supports 5-pin standard JTAG, cJTAG and Serial Wire Debug Port includes software for Windows, Linux and MacOSX requires Power Debug Module cJTAG and Serial Wire Debug require Power Debug Interface USB 2.0/USB 3.0, Power Debug Ethernet, PowerTrace or Power Debug II LA-7744A JTAG Debugger License for ARM10 Add.
OrderNo Code Text LA-7970X Trace License for ARM (Debug Cable) TRACE-LICENSE-ARM Supports for Embedded Trace Buffer (ETB) Extension applicable to the following debug cables (purchased separately): for LA-3743 (JTAG Debugger for ARMv8-A) for LA-7742 (JTAG Debugger for ARM9) for LA-7744 (JTAG Debugger for ARM10) for LA-7765 (JTAG Debugger for ARM11) for LA-7746 (JTAG Debugger for ARM7) for LA-7843 (JTAG Debugger for CORTEX-A/-R) please add the base serial number of your debug cable to your order LA-3717
ARM11 OrderNo Code Text LA-7765 JTAG Debugger for ARM11 (ICD) JTAG-ARM11 supports ARM11 (0.4 V - 5 V) supports 5-pin standard JTAG, cJTAG and Serial Wire Debug Port includes software for Windows, Linux and MacOSX requires Power Debug Module cJTAG and SerialWire Debug require Power Debug Interface USB 2.0/USB 3.
OrderNo Code Text LA-7765A JTAG Debugger License for ARM11 Add. JTAG-ARM11-A supports ARM11 Extension applicable to the following debug cables (purchased separately): 1.
Cortex-A/-R OrderNo Code Text LA-7843 JTAG Debugger for Cortex-A/-R (ARMv7) (ICD) JTAG-CORTEX-A/R supports ARM Cortex-A and Cortex-R (ARMv7, 32-bit) supports 5-pin standard JTAG, cJTAG and Serial Wire Debug Port (0.4 V - 5 V) includes software for Windows, Linux and MacOSX requires Power Debug Module cJTAG and Serial Wire Debug require Power Debug Interface USB 2.0/USB 3.0, Power Debug Ethernet, PowerTrace or Power Debug II LA-7843A JTAG Debugger License for Cortex-A/-R Add.
OrderNo Code Text LA-3717 Measuring Adapter JTAG 20 MES-AD-JTAG20 Adapter to measure JTAG signals by a logic analyzer or to disconnect single JTAG lines from the target LA-3881 ARM Converter ARM-20 to XILINX-14 CONV-ARM20/XILINX14 Converter to connect an ARM Debug Cable to a 14-pin JTAG connector found on Xilinx target boards LA-3862 ARM Conv. ARM-20, MIPI-34 to Mictor-38 CON-ARM/MIPI34-MIC Converter to connect the ARM Debug Cable or the CombiProbe to a Mictor connector on the target.
Order Information ARM7 Order No. Code Text LA-7746 LA-7746A LA-7746X LA-7748 LA-3780 LA-3770 LA-7747 LA-3726 LA-3717 LA-3862 JTAG-ARM7-20 JTAG-ARM7-A JTAG-ARM7-X JTAG-ARM-CON-20-TI14 JTAG-ARM-CON-20-TI20 CONV-ARM20/MIPI34 JTAG-ARM-CON-14-20 JTAG-ARM-CON-20-20 MES-AD-JTAG20 CON-ARM/MIPI34-MIC JTAG Debugger for ARM7 20 Pin Connector (ICD) JTAG Debugger License for ARM7 Add.
Order No. Code Text LA-3760A LA-7832A LA-3712A LA-7960X LA-7970X JTAG-XTENSA-A JTAG-ZSP400-A JTAG-ZSP500-A MULTICORE-LICENSE TRACE-LICENSE-ARM JTAG Debugger License for Xtensa Add. JTAG Debugger for ZSP400 DSP Core Additional JTAG Debugger for ZSP500 DSP Core Additional License for Multicore Debugging Trace License for ARM (Debug Cable) Order No.
Order No. Code Text LA-7836A LA-7789A LA-7850A LA-7817A LA-7845A LA-7774A LA-3844A LA-3774A LA-7847A LA-3760A LA-7832A LA-3712A LA-7960X JTAG-MMDSP-A JTAG-OAK-SEIB-A JTAG-R8051XC-A JTAG-SH4-A-20 JTAG-STARCORE-20-A JTAG-TEAK-JAM-20-A JTAG-TEAKLITE-4-A JTAG-TEAKLITE-III-A JTAG-TMS320C28X-A JTAG-XTENSA-A JTAG-ZSP400-A JTAG-ZSP500-A MULTICORE-LICENSE JTAG Debugger License for MMDSP JTAG Debugger for TeakLite/OAK SEIB (ICD) JTAG Debugger for R8051XC Add. JTAG Debugger License for SH2/SH3/SH4 Add.
ARM10 Order No. Code Text LA-7744 LA-7744A LA-7744X LA-7970X LA-3717 LA-3862 JTAG-ARM10 JTAG-ARM10-A JTAG-ARM10-X TRACE-LICENSE-ARM MES-AD-JTAG20 CON-ARM/MIPI34-MIC JTAG Debugger for ARM10 (ICD) JTAG Debugger License for ARM10 Add. JTAG Debugger Extension for ARM10 Trace License for ARM (Debug Cable) Measuring Adapter JTAG 20 ARM Conv.
ARM11 Order No. Code Text LA-7765 LA-7765A LA-7765X LA-7970X LA-3717 LA-3862 JTAG-ARM11 JTAG-ARM11-A JTAG-ARM11-X TRACE-LICENSE-ARM MES-AD-JTAG20 CON-ARM/MIPI34-MIC JTAG Debugger for ARM11 (ICD) JTAG Debugger License for ARM11 Add. JTAG Debugger Extension for ARM11 Trace License for ARM (Debug Cable) Measuring Adapter JTAG 20 ARM Conv.
Order No.
Cortex-A/-R Order No. Code Text LA-7843 LA-7843A LA-7843X LA-7970X LA-3717 LA-3881 LA-3862 JTAG-CORTEX-A/R JTAG-CORTEX-A/R-A JTAG-CORTEX-A/R-X TRACE-LICENSE-ARM MES-AD-JTAG20 CONV-ARM20/XILINX14 CON-ARM/MIPI34-MIC JTAG Debugger for Cortex-A/-R (ARMv7) (ICD) JTAG Debugger License for Cortex-A/-R Add. JTAG Debugger Extension for Cortex-A/-R Trace License for ARM (Debug Cable) Measuring Adapter JTAG 20 ARM Converter ARM-20 to XILINX-14 ARM Conv.
Order No. Code Text LA-3760A LA-7832A LA-3712A LA-7960X LA-7756A JTAG-XTENSA-A JTAG-ZSP400-A JTAG-ZSP500-A MULTICORE-LICENSE OCDS-TRICORE-A JTAG Debugger License for Xtensa Add.
