User Manual
6
DDR4 WHITE PAPER
Figure 5: Maximum mainstream module size.
Some quick math illustrates the increase in capacity: Sixteen of DDR3’s common 4Gb ICs
running in dual rank operation equals 64Gb (16 ICs * 4Gb IC), resulting in DDR3’s signature
8GB DIMM (64Gb / 8). However, DDR4 allows for 8Gb ICs and larger; sixteen of DDR4’s
8Gb ICs running in dual rank operation equals 128Gb (16 ICs * 8Gb IC), resulting in a DDR4
DIMM density of a healthy 16GB (128Gb / 8). DIMMs at this density are not expected to
reach the market until 2015, but the specification allows for them out of the gate, while
DDR3 has yet to hit this density in the mainstream.
Possibly most impressive is the forward-thinking nature of DDR4’s specification, though.
DDR4 is the first memory technology specified to handle three-dimensional silicon
stacking, or 3DS, allowing up to eight slave DRAMs to be stacked on top of a single master
DRAM and addressed through that master DRAM.
Finally, the increased density DDR4 oers allows for improvements in cost. An 8GB DDR3
DIMM requires sixteen 4Gb ICs running in dual rank, while an 8GB DDR4 DIMM, once 8Gb
ICs become available, would require only half that. This ignores the DDR4 specification
allowing up to 16Gb ICs.
Improved Reliability
One benefit of DDR4 not often mentioned but worth discussing is the overall improved
reliability and stability. While reliability and stability are appreciated on the consumer side
of the market, they’re vital on the enterprise side. The additions to the DDR4 specification
that address this benefit everyone.
First, DDR4 implements a CRC, or cyclic redundancy check. As operating frequencies scale,
the potential for write errors to memory increases. Employing the CRC allows for real-time
write error detection and can correct intermittent errors, as well as enabling more robust
error reporting to the system itself.
Command and address parity error detection and recovery have also been added to DDR4,
and changes to the DDR4 register allow it to block commands upon detection of a parity
error. While DDR3 would pass those commands on to the DRAM itself, DDR4 essentially
stops them at the gate.
Operating temperature is a well known inhibitor with most computing technologies, as
high temperatures can reduce signal clarity and produce errors. DDR4’s thermals can be
monitored and its timings adjusted to account for changes in temperature, though this is
only expected to be implemented in SODIMMs where heat becomes a more serious issue.