User`s guide

Index-3
approximations,
B-5
behavioral modeling expressions,
B-9
bias point,
B-7
bipolar transistors,
B-14
continuous equations,
B-4
DC sweep,
B-7
derivatives,
B-4
diagnostics,
B-15
dynamic range of time,
B-11
inductors and transformers,
B-13
Newton-Raphson requirements,
B-2
parasitic capacitances,
B-13
semiconductors,
B-7
switches,
B-8
transient analysis,
B-10
Create Subcircuit command,
4-7, 4-37
current source, controlled,
6-28, 6-46
cursors, Probe,
17-37
custom symbol creation for models,
5-13
using the Parts utility,
4-16, 5-11
using the symbol wizard,
5-6
D
DC analyses
displaying results in Probe,
2-11
see also DC sweep analysis, bias point detail anal-
ysis, small-signal DC transfer analysis, DC
sensitivity analysis
DC sensitivity analysis,
8-2, 9-13
introduction,
1-3
DC stimulus attribute,
9-5
DC sweep analysis,
8-2, 9-2
about,
9-3
curve families,
9-7
example,
2-10
introduction,
1-3
nested,
9-6
setting up,
2-10
stimulus,
9-5
DELAY stimulus attribute (digital),
14-16
derivative
problems,
B-4
device noise,
10-10, 10-12
total,
10-12
diagnostic problems,
B-15
differentiators (ABM),
6-7, 6-14
DIG_GND stimulus attribute (digital),
14-17
DIG_PWR stimulus attribute (digital),
14-17
DIGCLOCK digital stimulus symbol,
3-26, 14-5, 14-
16
DIGDRVF (strengths),
7-23
DIGDRVZ (strengths),
7-23
DIGERRDEFAULT (simulation option),
14-33
DIGERRLIMIT (simulation option),
14-33
DIGIFPWR digital power symbol,
3-22
DIGIOLVL (simulation option),
7-9
digital models,
7-29
digital parts
$G_DGND (reserved global net),
15-14
$G_DPWR (reserved global net),
15-14
CONSTRAINT primitive,
3-13
DIGIFPWR (power supply),
15-14
logic propagation delay selection,
14-21
LOGICEXP primitive,
3-13
PINDLY primitive,
3-13
vendor-supplied,
3-8
digital primitives,
7-3, 7-30
input (N device),
7-25
output (O device),
7-25
propagation delays, see timing model
syntax,
7-6
timing model, see timing model
digital simulation
charge storage nets,
7-18, 7-23
messages,
14-30
Probe waveform display,
17-25, 17-54, 17-57
propagation delays, see timing model
states,
7-21, 14-3
strengths,
7-21
timing model, see timing model
vector file,
19-6
worst-case timing,
16-2
digital values,
14-3
digital worst-case timing,
16-2
compared to analog worst-case,
16-2
convergence hazard,
14-32
cumulative ambiguity hazard,
14-32
glitch suppression,
14-32
DIGMNTYMX (simulation option),
16-3
DIGMNTYSCALE (simulation option),
7-12
DIGOVRDRV (simulation option),
7-23
DIGPOWER (I/O model),
7-18
DIGSTIM digital stimulus symbol,
3-26, 14-5, 14-8
DIGTYMXSCALE (simulation option),
7-12
diode,
17-52
diodes,
4-12, 8-8
DRVH (I/O model parameter),
15-13
DRVH (I/O model),
7-18, 7-22